SMJ320C6701_07 Datasheet, PDF (25/64 Pages) Texas Instruments – FLOATING-POINT DIGITAL SIGNAL PROCESSOR

clock PLL (continued)
SMJ320C6701
FLOATINGĆPOINT DIGITAL SIGNAL PROCESSOR
SGUS030B – APRIL 2000 – REVISED MAY 2001
Table 4. ’C6701 PLL Component Selection Table
CLKMODE
CLKIN
RANGE
(MHz)
CPU CLOCK
FREQUENCY
(CLKOUT1)
RANGE (MHz)
CLKOUT2
RANGE
(MHz)
R1
(Ω)
C1
(nF)
C2
(pF)
TYPICAL
LOCK TIME
(µs)^‡
x4
12.5–41.7
50–167
25–83.5
60.4
27
560
75
‡ _{Under some operating conditions, the maximum PLL lock time may vary as much as 150% from the specified typical value. For example, if the}
typical lock time is specified as 100 µs, the maximum value may be as long as 250 µs.
3.3V
PLLV
PLLFREQ3
PLLFREQ2
PLLFREQ1
(see Table 3)
C3
10 mF
C4
0.1 mF
CLKMODE0
CLKMODE1
CLKIN
PLLMULT
PLL
PLLCLK
CLKIN
LOOP FILTER
Internal to ’C6701
1
CPU
0
CLOCK
CLKMODE1
0
0
1
1
Available Multiply Factors
CLKMODE0
PLL Multiply
Factors
0
x1(BYPASS)
1
Reserved
0
Reserved
1
x4
CPU Clock
Frequency
f(CPUCLOCK)
1 x f(CLKIN)
Reserved
Reserved
4 x f(CLKIN)
C2
C1
R1
NOTES: A. Keep the lead length and the number of vias between the PLLF pin, the PLLG pin, and R1, C1, and C2 to a minimum. In addition,
place all PLL external components (R1, C1, C2, C3, C4, and the EMI Filter) as close to the ’C6000 device as possible. For the best
performance, TI recommends that all the PLL external components be on a single side of the board without jumpers, switches, or
components other than the ones shown.
B. For reduced PLL jitter, maximize the spacing between switching signals and the PLL external components (R1, C1, C2, C3, C4,
and the EMI Filter).
C. The 3.3-V supply for the EMI filter must be from the same 3.3-V power plane supplying the I/O voltage, DVDD.
Figure 5. External PLL Circuitry for Either PLL x4 Mode or x1 (Bypass) Mode
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