SMJ320C6701_07 Datasheet, PDF (42/64 Pages) Texas Instruments – FLOATING-POINT DIGITAL SIGNAL PROCESSOR

SMJ320C6701
FLOATINGĆPOINT DIGITAL SIGNAL PROCESSOR
SGUS030B – APRIL 2000 – REVISED MAY 2001
HOLD/HOLDA TIMING
timing requirements for the hold/hold acknowledge cycles^† (see Figure 24)
’C6701-14
NO.
’C6701-16
UNIT
MIN MAX
1 tsu(HOLDH-CKO1H) Setup time, HOLD high before CLKOUT1 high
5
ns
2 th(CKO1H-HOLDL) Hold time, HOLD low after CLKOUT1 high
2
ns
† _{HOLD is synchronized internally. Therefore, if setup and hold times are not met, it will either be recognized in the current cycle or in the next cycle.}
Thus, HOLD can be an asynchronous input.
switching characteristics for the hold/hold acknowledge cycles^‡ (see Figure 24)
NO.
PARAMETER
’C6701-14
’C6701-16
UNIT
MIN MAX
3 tR(HOLDL-EMHZ)
Response time, HOLD low to EMIF high impedance
4P
§
ns
4 tR(EMHZ-HOLDAL)
Response time, EMIF high impedance to HOLDA low
2P
ns
5 tR(HOLDH-HOLDAH) Response time, HOLD high to HOLDA high
4P 7P
ns
6 td(CKO1H-HOLDAL)
Delay time, CLKOUT1 high to HOLDA valid
1
8
ns
7 td(CKO1H-BHZ)
Delay time, CLKOUT1 high to EMIF Bus high impedance^¶
*1
*8
ns
8 td(CKO1H-BLZ)
Delay time, CLKOUT1 high to EMIF Bus low impedance^¶
*1 *12
ns
9 tR(HOLDH-BLZ)
Response time, HOLD high to EMIF Bus low impedance^¶
3P 6P
ns
‡ _{P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns.}
§ _{All pending EMIF transactions are allowed to complete before HOLDA is asserted. The worst cases for this is an asynchronous read or write}
with external ARDY used or a minimum of eight consecutive SDRAM reads or writes when RBTR8 = 1. If no bus transactions are occurring, then
the minimum delay time can be achieved. Also, bus hold can be indefinitely delayed by setting the NOHOLD = 1.
¶ _{EMIF Bus consists of CE[3:0], BE[3:0], ED[31:0], EA[21:2], ARE, AOE, AWE, SSADS, SSOE, SSWE, SDA10, SDRAS, SDCAS, and SDWE.}
*This parameter is not tested.
DSP Owns Bus
External Requester
DSP Owns Bus
CLKOUT1
HOLD
4
3
2
1
6
5
9
2
1
6
HOLDA
7
EMIF Bus^†
’C6701
Ext Req
8
’C6701
† _{EMIF Bus consists of CE[3:0], BE[3:0], ED[31:0], EA[21:2], ARE, AOE, AWE, SSADS, SSOE, SSWE, SDA10, SDRAS, SDCAS, and SDWE.}
Figure 24. HOLD/HOLDA Timing
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