DAC8574 Datasheet, PDF (5/40 Pages) Texas Instruments – QUAD, 16-BIT, LOW-POWER, VOLTAGE OUTPUT, I2C INTERFACE DIGITAL-TO-ANALOG CONVERTER

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DAC8574
SLAS377A – JANUARY 2003 – REVISED JUNE 2003
TIMING CHARACTERISTICS (continued)
V_DD = 2.7 V to 5.5 V, R_L = 2 kΩ to GND; all specifications -40°C to +105°C, unless otherwise specified.
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
t_RCL1
t_FCL
t_RDA
t_FDA
Standard mode
Rise time of SCL signal after a
Fast mode
repeated START condition
and after an acknowledge BIT ^{High-speed mode, C}B ^{= 100 pF max}
High-speed mode, C_B = 400 pF max
Standard mode
Fall time of SCL signal
Fast mode
High-speed mode, C_B = 100 pF max
High-speed mode, C_B = 400 pF max
Standard mode
Rise time of SDA signal
Fast mode
High-speed mode, C_B = 100 pF max
High-speed mode, C_B = 400 pF max
Standard mode
Fall time of SDA signal
Fast mode
High-speed mode, C_B = 100 pF max
High-speed mode, C_B = 400 pF max
Standard mode
20 × 0.1C_B
20 × 0.1C_B
10
20
20 × 0.1C_B
20 × 0.1C_B
10
20
20 × 0.1C_B
20 × 0.1C_B
10
20
20 × 0.1C_B
20 × 0.1C_B
10
20
4.0
t_SU; t_STO
Setup time for STOP condition
Fast mode
600
High-speed mode
160
C_B
Capacitive load for SDA and
SCL
t_SP
Pulse width of spike sup-
pressed
Fast mode
High-speed mode
Noise margin at the HIGH
V_NH
level for each connected de-
vice (including hysteresis)
Standard mode
Fast mode
High-speed mode
0.2 V_DD
Noise margin at the LOW level
V_NL
for each connected device
(including hysteresis)
Standard mode
Fast mode
High-speed mode
0.1 V_DD
MAX
1000
300
80
160
300
300
40
80
1000
300
80
160
300
300
80
160
400
50
10
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
ns
pF
ns
ns
V
V
5