DAC8574 Datasheet, PDF (28/40 Pages) Texas Instruments – QUAD, 16-BIT, LOW-POWER, VOLTAGE OUTPUT, I2C INTERFACE DIGITAL-TO-ANALOG CONVERTER

DAC8574
SLAS377A – JANUARY 2003 – REVISED JUNE 2003
www.ti.com
CURRENT CONSUMPTION
The DAC8574 typically consumes 225 µA at V_DD = 5 V and 200 µA at V_DD = 3 V for each active channel,
including reference current consumption. Additional current consumption can occur at the digital inputs if V_IH <<
V_DD. For most efficient power operation, CMOS logic levels are recommended at the digital inputs to the DAC. In
power-down mode, typical current consumption is 200 nA. A delay time of 10 to 20 ms after a power-down
command is issued to the DAC is typically sufficient for the power-down current to drop below 10 µA.
DRIVING RESISTIVE AND CAPACITIVE LOADS
The DAC8574 output stage is capable of driving loads of up to 1000 pF while remaining stable. Within the offset
and gain error margins, the DAC8574 can operate rail-to-rail when driving a capacitive load. Resistive loads of 2
kΩ can be driven by the DAC8574 while achieving very good load regulation. Load regulation error increases as
the output voltage approaches each rail. When the outputs of the DAC are driven to the positive rail under
resistive loading, the PMOS transistor of each Class-AB output stage can enter into the linear region. When this
occurs, the added IR voltage drop deteriorates the linearity performance of the DAC. This only occurs within
approximately the top 20 mV of the DAC’s digital input-to-voltage output transfer characteristic. The reference
voltage applied to the DAC8574 may be reduced below the supply voltage applied to V_DD in order to eliminate
this condition if good linearity is a requirement at full scale (under resistive loading conditions).
CROSSTALK AND AC PERFORMANCE
The DAC8574 architecture uses separate resistor strings for each DAC channel in order to achieve ultra-low
crosstalk performance. DC crosstalk seen at one channel during a full-scale change on the neighboring channel
is typically less than 0.5 LSBs. The ac crosstalk measured (for a full-scale, 1 kHz sine wave output generated at
one channel, and measured at the remaining output channel) is typically under -100 dB. In addition, the
DAC8574 can achieve typical ac performance of 96 dB signal-to-noise ratio (SNR) and 65 dB total harmonic
distortion (THD), making the DAC8574 a solid choice for applications requiring high SNR at output frequencies at
or below 4 kHz.
OUTPUT VOLTAGE STABILITY
The DAC8574 exhibits excellent temperature stability of ±3 ppm/°C typical output voltage drift over the specified
temperature range of the device. This enables the output voltage of each channel to stay within a ±25 µV window
for a ±1°C ambient temperature change. Good power-supply rejection ratio (PSRR) performance reduces supply
noise present on V_DD from appearing at the outputs to well below 10 µV-s. Combined with good dc noise
performance and true 16-bit differential linearity, the DAC8574 becomes a perfect choice for closed-loop control
applications.
SETTLING TIME AND OUTPUT GLITCH PERFORMANCE
Settling time to within the 16-bit accurate range of the DAC8574 is achievable within 10 µs for a full-scale code
change at the input. Worst case settling times between consecutive code changes is typically less than 2 µs. The
high-speed serial interface of the DAC8574 is designed in order to support up to 188ksps update rate. For
full-scale output swings, the output stage of each DAC8574 channel typically exhibits less than 100 mV of
overshoot and undershoot when driving a 200 pF capacitive load. Code-to-code change glitches are extremely
low (~10 µV) given that the code-to-code transition does not cross an Nx4096 code boundary. Due to internal
segmentation of the DAC8574, code-to-code glitches occur at each crossing of an Nx4096 code boundary.
These glitches can approach 100mVs for N = 15, but settle out within ~2 µs.
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