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| DAC8574 Datasheet, PDF (37/40 Pages) Texas Instruments – QUAD, 16-BIT, LOW-POWER, VOLTAGE OUTPUT, I2C INTERFACE DIGITAL-TO-ANALOG CONVERTER | |||
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www.ti.com
DAC8574
SLAS377A â JANUARY 2003 â REVISED JUNE 2003
APPLICATION INFORMATION (continued)
EXAMPLE 14: Broadcast update command. All channels of all DAC8574s update with previously stored temporary register data.
ADDRESS [7...0]
C [7...0]
M [7...0]
L [7...0]
START
1001 0000
ACK 0011 0000 ACK
XXXX XXXX
ACK
XXXX XXXX ACK STOP
Previous DAC output voltages are valid for all channels, all DAC8574s
New data is valid
EXAMPLE 15: Broadcast Data. All channels of all DAC8574s get set to code 7.
ADDRESS [7...0]
C [7...0]
M [7...0]
L [7...0]
START
1001 0000
ACK 0011 0001
ACK
0000 0000
ACK
0000 0111 ACK STOP
Previous DAC output voltages are valid for all channels, all DAC8574s
All Vouts = 7 x 76
µV
EXAMPLE 16: Broadcast Power-Down. All channels of all DAC8574s get powered down with output impedance of 1 k⦠to ground.
ADDRESS [7...0]
C [7...0]
M [7...0]
L [7...0]
START
1001 0000
ACK 0011 0001
ACK
0100 0000
ACK
0000 0000 ACK STOP
Previous DAC output voltages are valid for all channels, all DAC8574s
All Vouts = GND
I2C Read-back Examples (A0, A1, A2, A3 and LDAC pins tied to GND):
EXAMPLE 17: Read back channel A power-down bits and 16-bit channel A data. V denotes valid logic.
ADDRESS [7...0]
C [7...0]
REPEATED
ADDRESS
START
1001 1000
ACK
0001 0001
ACK
START
1001 1001
PWD [7...0]
MASTER
MSB [7...0] MASTER
LSB [7...0]
MASTER
VV11 1111
ACK
VVVV VVVV ACK
VVVV VVVV NOT ACK
EXAMPLE 18: Read back channel B power-down bits and 16-bit channel B data. V denotes valid logic.
ADDRESS [7...0]
C [7...0]
REPEATED
ADDRESS
START
1001 1000
ACK
0001 0011
ACK
START
1001 1001
PWD [7...0]
MASTER
MSB [7...0] MASTER
LSB [7...0]
MASTER
VV11 1111
ACK
VVVV VVVV ACK
VVVV VVVV
NOT ACK
EXAMPLE 19: Read back channel C power-down bits and 16-bit channel C data. V denotes valid logic.
ADDRESS [7...0]
C [7...0]
REPEATED
ADDRESS
START
1001 1000
ACK
0001 0101
ACK
START
1001 1001
PWD [7...0]
MASTER
MSB [7...0] MASTER
LSB [7...0]
MASTER
VV11 1111
ACK
VVVV VVVV ACK
VVVV VVVV
NOT ACK
EXAMPLE 20: Read back channel D power-down bits and 16-bit channel D data. V denotes valid logic.
ADDRESS [7...0]
C [7...0]
REPEATED
ADDRESS
START
1001 1000
ACK
0001 0011
ACK
START
1001 1001
PWD [7...0]
MASTER
MSB [7...0] MASTER
LSB [7...0]
MASTER
VV11 1111
ACK
VVVV VVVV ACK
VVVV VVVV
NOT ACK
EXAMPLE 21: Read back 16-bit channel D data only. V denotes valid logic.
ADDRESS [7...0]
C [7...0]
REPEATED
ADDRESS
START
1001 1000
ACK
0001 0110
ACK
START
1001 1001
MSB [7...0]
MASTER
LSB [7...0]
MASTER
VVVV VVVV
ACK
VVVV VVVV
NOT ACK
ACK
ACK
ACK
ACK
ACK
37
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