DAC8574 Datasheet, PDF (19/40 Pages) Texas Instruments – QUAD, 16-BIT, LOW-POWER, VOLTAGE OUTPUT, I2C INTERFACE DIGITAL-TO-ANALOG CONVERTER

www.ti.com
DAC8574
SLAS377A – JANUARY 2003 – REVISED JUNE 2003
C7 C6
C5
A3 A2 Load1
(Address Sel-
ect)
(A3 and A2
should corre- 0
spond to the
package ad-
dress set via
pins A3 and
0
A2.)
0
C4
Load0
0
0
0
C3
Don’t
Care
Table 2. Control Byte
C2
C1
C0
Ch Sel 1 Ch Sel 0 PD0
MSB7
MSB
(PD1)
MSB6
MSB-1
(PD2)
X
0
X
0
X
1
0
0
1
0
0
0
Data
Data
Data
X
X
0
0
0
0
X
1
1
0
Data
(00, 01, 10, or 11)
X
1
see Table 8
0
1
(00, 01, 10, or 11)
X
0
Data
0
1
(00, 01, 10, or 11)
X
1
see Table 8
1
0
(00, 01, 10, or 11)
X
0
Data
1
0
(00, 01, 10, or 11)
X
1
see Table 8
Broadcast Modes (controls up to 4 devices on a single serial bus)
1
1
X
0
X
X
X
X
X
1
1
X
1
X
X
1
1
X
1
X
0
Data
X
1
see Table 8
MSB5...
MSB-2
...LSB
0
0
0
0
DESCRIPTION
Write to temporary
register A (TRA) with
data
Write to temporary
register B (TRB) with
data
Write to temporary
register C (TRC) with
data
Write to temporary
register D (TRD) with
data
Write to TRx (selected
by C2 &C1
w/Powerdown Com-
mand
Write to TRx (selected
by C2 &C1 and load
DACx w/data
Power-down DACx
(selected by C2 and
C1)
Write to TRx (selected
by C2 &C1 w/ data and
load all DACs
Power-down DACx
(selected by C2 and
C1) & load all DACs
Update all DACs, all
devices with previously
stored TRx data
Update all DACs, all
devices with MSB[7:0]
and LSB[7:0] data
Power-down all DACs,
all devices
Most Significant Byte
Most Significant Byte MSB[7:0] consists of eight most significant bits of 16-bit unsigned binary D/A conversion
data. C0=1, MSB[7], MSB[6] indicate a powerdown operation as shown in Table 8.
Least Significant Byte
Least Significant Byte LSB[7:0] consists of the 8 least significant bits of the 16bit unsigned binary D/A conversion
data. DAC8574 updates at the falling edge of the acknowledge signal that follows the LSB[0] bit.
Default Readback Condition
If the user initiates a readback of a specified channel without first writing data to that specified channel, the
default readback is all zeros, since the readback register is initialized to 0 during the power on reset phase.
19