DAC8574 Datasheet, PDF (17/40 Pages) Texas Instruments – QUAD, 16-BIT, LOW-POWER, VOLTAGE OUTPUT, I2C INTERFACE DIGITAL-TO-ANALOG CONVERTER

www.ti.com
Recognize START or
REPEATED START
Condition
SDA
MSB
Address
Generate ACKNOWLEDGE
Signal
Acknowledgement
Signal From Slave
DAC8574
SLAS377A – JANUARY 2003 – REVISED JUNE 2003
Recognize STOP or
REPEATED START
Condition
P
Sr
R/W
SCL
S
or
Sr
1
2
START or
Repeated START
Condition
7
8
9
ACK
1
2
Clock Line Held Low While
Interrupts are Serviced
Figure 50. Bus Protocol
3-8
9
Sr
ACK
or
P
STOP or
Repeated START
Condition
DAC8574 I²C Update Sequence
The DAC8574 requires a start condition, a valid I²C address, a control byte, an MSB byte, and an LSB byte for a
single update. After the receipt of each byte, DAC8574 acknowledges by pulling the SDA line low during the high
period of a single clock pulse. A valid I²C address selects the DAC8574. The control byte sets the operational
mode of the selected DAC8574. Once the operational mode is selected by the control byte, DAC8574 expects an
MSB byte followed by an LSB byte for data update to occur. DAC8574 performs an update on the falling edge of
the acknowledge signal that follows the LSB byte.
Control byte needs not to be resent until a change in operational mode is required. The bits of the control byte
continuously determine the type of update performed. Thus, for the first update, DAC8574 requires a start
condition, a valid I²C address, a control byte, an MSB byte and an LSB byte. For all consecutive updates,
DAC8574 needs an MSB byte and an LSB byte as long as the control command remains the same.
Using the I²C high-speed mode (f_scl= 3.4 MHz), the clock running at 3.4 MHz, each 16-bit DAC update other than
the first update can be done within 18 clock cycles (MSB byte, acknowledge signal, LSB byte, acknowledge
signal), at 188.88 KSPS. Using the fast mode (f_scl= 400 kHz), clock running at 400 kHz, maximum DAC update
rate is limited to 22.22 KSPS. Once a stop condition is received DAC8574 releases the I²C bus and awaits a new
start condition.
Address Byte
MSB
LSB
1
0
0
1
1
A1
A0 R/W
The address byte is the first byte received following the START condition from the master device. The first five
bits (MSBs) of the address are factory preset to 10011. The next two bits of the address are the device select
bits A1 and A0. The A1, A0 address inputs can be connected to V_DD or digital GND, or can be actively driven by
TTL/CMOS logic levels. The device address is set by the state of these pins during the power-up sequence of
the DAC8574. Up to 16 devices (DAC8574) can still be connected to the same I²C-Bus.
17