DAC8574 Datasheet, PDF (25/40 Pages) Texas Instruments – QUAD, 16-BIT, LOW-POWER, VOLTAGE OUTPUT, I2C INTERFACE DIGITAL-TO-ANALOG CONVERTER

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DAC8574
SLAS377A – JANUARY 2003 – REVISED JUNE 2003
Master Receiver Reading From a Slave Transmitter (DAC8574) in Standard/Fast Modes
When reading data back from the DAC8574, the user begins with an address byte (with R/W = 0) after which the
DAC8574 will acknowledge by pulling SDA low. This address byte is usually followed by the Control Byte, which
is also acknowledged by the DAC8574. Following this there is a REPEATED START condition by the Master and
the address is resent with (R/W = 1). This is acknowledged by the DAC8574, indicating that it is prepared to
transmit data. Two or three bytes of data are then read back from the DAC8574, depending on the (PD0-Bit).
The value of Buff-Sel1 and Buff-Sel0 determines, which channel data is read back. A STOP Condition follows.
With the (PD0-Bit = 0) the DAC8574 transmits 2 bytes of data, HIGH-BYTE followed by the LOW-BYTE (refer to
Table 2. Data Readback Mode - 2 bytes).
With the (PD0-Bit = 1) the DAC8574 transmits 3 bytes of data, POWER-DOWN-BYTE followed by the
HIGH-BYTE followed by the LOW-BYTE (refer to Table 2. Data Readback Mode - 3 bytes).
Table 6. Read Sequence in F/S Mode
DATA READBACK MODE - 2 BYTES
Transmitter MSB
6
5
Master
Master
1
0
0
DAC8574
Master
A3
A2 Load 1
DAC8574
Master
Master
1
0
0
DAC8574
DAC8574
D15
D14
D13
Master
DAC8574
D7
D6
D5
Master
Master
DATA READBACK MODE - 3 BYTES
Transmitter MSB
6
5
Master
Master
1
0
0
DAC8574
Master
A3
A2 Load 1
DAC8574
Master
Master
1
0
0
DAC8574
DAC8574
PD1 PD2
1
Master
DAC8574
D15
D14
D13
Master
DAC8574
D7
D6
D5
Master
Master
4
3
2
Start
1
1
A1
DAC8574 Acknowledges
Load 0
x
Buff Sel 1
DAC8574 Acknowledges
Repeated Start
1
1
A1
DAC8574 Acknowledges
D12
D11
D10
Master Acknowledges
D4
D3
D2
Master Not Acknowledges
Stop or Repeated Start ⁽¹⁾
1
A0
Buff Sel 0
A0
D9
D1
4
3
2
Start
1
1
A1
DAC8574 Acknowledges
Load 0
x
Buff Sel 1
DAC8574 Acknowledges
Repeated Start
1
1
A1
DAC8574 Acknowledges
1
1
1
Master Acknowledges
D12
D11
D10
Master Acknowledges
D4
D3
D2
Master Not Acknowledges
Stop or Repeated Start ⁽¹⁾
1
A0
Buff Sel 0
A0
1
D9
D1
LSB
R/W
Comment
Begin sequence
Write addressing (R/W=0)
PD0 Control byte (PD0=0)
R/W Read addressing (R/W = 1)
D8
Reading data word, high byte
D0
Reading data word, low byte
Master signal end of read
Done
LSB Comment
Begin sequence
R/W Write addressing (R/W=0)
PD0 Control byte (PD0=1)
R/W Read addressing (R/W = 1)
1
Read power down byte
D8
Reading data word, high byte
D0
Reading data word, low byte
Master signal end of read
Done
(1) _{Use repeated start to secure bus operation and loop back to the stage of write addressing for next Write.}
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