DAC8574 Datasheet, PDF (26/40 Pages) Texas Instruments – QUAD, 16-BIT, LOW-POWER, VOLTAGE OUTPUT, I2C INTERFACE DIGITAL-TO-ANALOG CONVERTER

DAC8574
SLAS377A – JANUARY 2003 – REVISED JUNE 2003
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Master Receiver Reading From a Slave Transmitter (DAC8574) in HS-Mode
When reading data to the DAC8574 in HS-MODE, the master begins to transmit, what is called the HS-Master
Code (0000 1XXX) in F/S-mode. No device is allowed to acknowledge the HS-Master Code, so the HS-Master
Code is followed by a NOT acknowledge.
The Master then switches to HS-mode and issues a REPEATED START condition, followed by the address byte
(with R/W = 0) after which the DAC8574 acknowledges by pulling SDA low. This address byte is usually followed
by the control byte, which is also acknowledged by the DAC8574.
Then there is a REPEATED START condition initiated by the master and the address is resent with (R/W = 1).
This is acknowledged by the DAC8574, indicating that it is prepared to transmit data. Two or Three bytes of data
are then read back from the DAC8574, depending on the (PD0-Bit). The value of Buff-Sel1 and Buff-Sel0
determines, which channel data is read back. A STOP condition follows.
With the (PD0-Bit = 0) the DAC8574 transmits 2 bytes of data, HIGH-BYTE followed by LOW-BYTE (refer to
Table 7 HS-Mode Readback Sequence).
With the (PD0-Bit = 1) the DAC8574 transmits 3 bytes of data, POWER-DOWN-BYTE followed by the
HIGH-BYTE followed by the LOW-BYTE (refer to Table 7 HS-Mode Readback Sequence).
Table 7. Master Receiver Reading Slave Transmitter (DAC8574) in HS-Mode
HS MODE READBACK SEQUENCE
Transmitter MSB
6
5
Master
Master
0
0
0
NONE
Master
Master
DAC8574
Master
DAC8574
Master
Master
DAC8574
DAC8574
Master
DAC8574
Master
DAC8574
Master
Master
1
0
0
A3
A2 Load 1
1
0
0
PD1 PD2
1
D15 D14 D13
D7
D6
D5
4
3
2
Start
0
1
X
Not Acknowledge
Repeated Start
1
1
A1
DAC8574 Acknowledges
Load 0 X Buff Sel 1
DAC8574 Acknowledges
Repeated Start
1
1
A1
DAC8574 Acknowledges
1
1
1
Master Acknowledges
D12 D11
D10
Master Acknowledges
D4
D3
D2
Master Not Acknowledges
Stop or Repeated Start
1
X
A0
Buff Sel 0
A0
1
D9
D1
LSB
X
R/W
PD0
R/W
1
D8
D0
Comment
Begin sequence
HS Mode Master Code
No device may acknowledge HS
master code
Write addressing (R/W=0)
Control byte (PD0 = 1)
Read addressing (R/W=1)
Power-down byte
Reading data word, high byte
Reading data word, low byte
Master signal end of read
Done
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