DAC8574 Datasheet, PDF (14/40 Pages) Texas Instruments – QUAD, 16-BIT, LOW-POWER, VOLTAGE OUTPUT, I2C INTERFACE DIGITAL-TO-ANALOG CONVERTER

DAC8574
SLAS377A – JANUARY 2003 – REVISED JUNE 2003
THEORY OF OPERATION
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D/A SECTION
The architecture of the DAC8574 consists of a string DAC followed by an output buffer amplifier. Figure 45
shows a generalized block diagram of the DAC architecture.
DAC Register
V_REFH
70 kW
50 kW
Ref+
Resistor String
Ref-
50 kW
_
+
V_OUT
V_REFL
Figure 45. R-String DAC Architecture
The input coding to the DAC8574 is unsigned binary, which gives the ideal output voltage as:
V_OUT + V_REFL ) (V_REFH * V_REFL)
D
65536
(1)
Where D = decimal equivalent of the binary code that is loaded to the DAC register; it can range from 0 to
65535.
RESISTOR STRING
The resistor string section is shown in Figure 46. It is basically a divide-by-2 resistor, followed by a string of
resistors, each of value R. The code loaded into the DAC register determines at which node on the string the
voltage is tapped off to be fed into the output amplifier by closing one of the switches connecting the string to the
amplifier. Because the architecture consists of a string of resistors, it is specified monotonic.
V_REFH
To Output
Amplifier
R
R
R
R
Figure 46. Typical Resistor String
V_REFL
Output Amplifier
The output buffer is a gain-of-2 noninverting amplifiers, capable of generating rail-to-rail voltages on its output,
which gives an output range of 0V to V_DD. It is capable of driving a load of 2 kΩ in parallel with 1000 pF to GND.
The source and sink capabilities of the output amplifier can be seen in the typical curves. The slew rate is 1 V/µs
with a half-scale settling time of 8 µs with the output unloaded.
I²C Interface
I²C is a 2-wire serial interface developed by Philips Semiconductor (see I²C-Bus Specification, Version 2.1,
January 2000). The bus consists of a data line (SDA) and a clock line (SCL) with pullup structures. When the bus
is idle, both SDA and SCL lines are pulled high. All the I²C compatible devices connect to the I²C bus through
open drain I/O pins, SDA and SCL. A master device, usually a microcontroller or a digital signal processor,
controls the bus. The master is responsible for generating the SCL signal and device addresses. The master also
generates specific conditions that indicate the START and STOP of data transfer. A slave device receives and/or
transmits data on the bus under control of the master device.
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