DAC8574 Datasheet, PDF (33/40 Pages) Texas Instruments – QUAD, 16-BIT, LOW-POWER, VOLTAGE OUTPUT, I2C INTERFACE DIGITAL-TO-ANALOG CONVERTER

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DAC8574
SLAS377A – JANUARY 2003 – REVISED JUNE 2003
APPLICATION INFORMATION (continued)
Digital Correction of DAC Errors
For open-loop applications requiring improved accuracy, offset and gain errors of the DAC8574 can be measured
and digitally corrected. To avoid waveform clipping, it is recommended to make the offset and gain error
measurements at codes 1024 and 64512 respectively. The total error of DAC8574 is dominated by gain and
offset errors, and it can be improved by an order of magnitude using the following digital correction:
DIN = DDIN – OE – (FSE – OE) × (DDIN – 1024) ÷ 64512
where:
DIN = Digital input code to the DAC after offset and gain correction
DDIN = Digital input code to the DAC before offset and gain correction
OE = measured DAC error at code 1024 (in LSBs)
FSE = measured DAC error at code 64512 (in LSBs)
If division operation is not feasible, FSE measurement can be done at code 32768 instead of code 64512.
Division by 32768 implies a 15-bit arithmetic right shift. Improvements to the transfer curve are still significant.
DAC8574 integral linearity error is well within ±5 mV, therefore it only has a secondary effect on total DAC error.
Using piece-wise linear approximation, and non-volatile memory, integral linearity errors of DAC8574 can also be
digitally corrected. Consult TI applications engineering for details.
64 Channel Operation
DAC8574 is designed to facilitate high channel count operation. DAC8574 supports multichannel simultaneous
synchronous update up to 16 DAC8574 devices for up to 64 channels on a single I²C bus. Working with multiple
DAC8574s, single channel DAC8571s can be used on the same bus to obtain odd channel counts, or quad
channel DAC7574s can be used if some channels only need 12 bits of resolution.
Data or power down can be loaded to temporary registers of each channel serially and a single broadcast
operation can be used to update all channels of all devices simultaneously with previously stored data or
power-down condition. Another feature useful for system start-up or system shut-down is to broadcast the same
data (or power-down condition) to all channels with a single broadcast command.
All multichannel system updates are performed at the falling edge of the acknowledge signal that follows the
least significant byte.
The 64-channel operation requires 6-bit address decoding. 4-bit address decoding is used to support 16
DAC8574 devices on the same bus and 2-bit address decoding is used to select one out of four channels of a
DAC8574. 4-bit address decoding that selects one out of 16 DAC8574 devices is done as follows: To save I²C
address space, 2-bits (A0 and A1) are used for I²C address decoding, and two additional bits (A2 and A3) are
used for local address decoding. Up to 4 DAC8574 devices using the same I²C address can be connected on the
same I²C bus. These four devices with the same I²C address can be locally decoded using A2 and A3 pins. If
multiple devices use the same I²C address, multiple devices acknowledge at the same time. However, in order
for a particular device to respond to a command, the states of the first two bits of the control word C7 and C6
must match the states of A3 and A2 pins. Four devices per I²C address and four distinct I²C addresses enable
16 devices on the same bus.
The four address pins should be set at power-up, and address bits must be set to match a particular device’s
address pins. To decode up to 16 DAC8574 devices, the logic states of A3, A2, A1, A0 address pins and C7, C6,
A1, A0 address bits should be set as shown in Table 9.
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