SMJ44C251B Datasheet, PDF (47/53 Pages) Texas Instruments – 262144 BY 4-BIT MULTIPORT VIDEO RAM

SMJ44C251B
262144 BY 4-BIT
MULTIPORT VIDEO RAM
SGMS058A – MARCH 1995 – REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
RAS
CAS
A0 – A8
TRG
DSF
Row Tap1
(low )
Row Tap1
(high)
Row Tap2
(low )
Row Tap2
(high)
CASE I
SC
QSF
Tap1
(low )
Bit Tap1
255 (high)
Bit Tap2
Bit
511 (low )
255
CASE II
SC
QSF
Tap1
(low )
Bit Tap1
255 (high)
Bit Tap2
Bit
511 (low )
255
CASE III
SC
QSF
Tap1 Bit Tap1
(low ) 255 (high)
Bit Tap2
Bit
511 (low )
255
Normal Read Transfer
Split Register to the
High Half of the
Data Register
Split Register to the
Low Half of the
Data Register
Split Register to the
High Half of the
Data Register
NOTES: A. In order to achieve proper split-register operation, a normal read transfer should be performed before the first split-register transfer
cycle. This is necessary to initialize the data register and the starting tap location. First serial access can then begin either after the
normal read-transfer cycle (CASE I), during the first split-register cycle (CASE II), or even after the first split-register transfer cycle
(CASE III). There is no minimum requirement of SC clock between the normal read-transfer cycle and the first split-register cycle.
B. A split register transfer into the inactive half is not allowed until td(MSRL) is met. td(MSRL) is the minimum delay time between the rising
edge of the serial clock of the last bit (bit 255 or 511) and the falling edge of RAS of the split-register transfer cycle into the inactive
half. After td(MSRL) is met, the split-register transfer into the inactive half must also satisfy the td(RHMS) requirement. td(RHMS) is the
minimum delay time between the rising edge of RAS of the split-register transfer cycle into the inactive half and the rising edge of
the serial clock of the last bit (bit 255 or 511). There is a minimum requirement of one rising edge of SC clock between two split-register
transfer cycles.
Figure 35. Split-Register-Transfer Operating Sequence
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