SMJ44C251B Datasheet, PDF (15/53 Pages) Texas Instruments – 262144 BY 4-BIT MULTIPORT VIDEO RAM

normal-read transfer (continued)
RAS
Early-Load Read Transfer
CAS
A0 – A8
TRG
Row Tap Point
SC
Bit
Tap
512
Bit
SMJ44C251B
262144 BY 4-BIT
MULTIPORT VIDEO RAM
SGMS058A – MARCH 1995 – REVISED JUNE 1995
Real-Time-Reload Read Transfer
Late-Load Read Transfer
Row Tap Point
Bit
Bit
Tap
510
511
Bit
Row Tap Point
Bit
Bit
Tap
510
511
Bit
Figure 7. Normal-Read-Transfer Timings
split-register-read transfer
In split-register-read-transfer operation, the serial-data register is split into halves. The low half contains bits
0 – 255, and the high half contains 256 – 511. While one half is being read out of the SAM port, the other half can
be loaded from the memory array.
To invoke a split-register read-transfer cycle, DSF is brought high, TRG is brought low, and both are latched at
the falling edge of RAS. Nine row-address bits (A0 – A8) are also latched at the falling edge of RAS to select
one of the 512 rows available for the transfer. The nine column-address bits (A0 –A8) are latched at the falling
edge of CAS, where address bits A0 – A7 select one of the 255 tap points in the specified half of SAM and
address bit A8 selects which half is to be transferred. If A8 is a logic low, the low half is transferred. If A8 is a
logic high, the high half is transferred. SAM locations 255 and 511 cannot be used as tap points.
A normal-read transfer must precede the split-register-read transfer to ensure proper operation. After the
normal-read-transfer cycle, the first split-register read transfer can follow immediately without any minimum SC
requirement. However, there is a minimum requirement of a rising edge of SC between split-register
read-transfer cycles.
QSF indicates which half of the SAM is being accessed during serial-access operation. When QSF is low, the
serial-address pointer is accessing the lower (least significant) 256 bits of the SAM. When QSF is high, the
pointer is accessing the higher (most significant) 256 bits of the SAM. QSF changes state upon completing a
normal-read-transfer cycle. The tap point loaded during the current transfer cycle determines the state of QSF.
In split-register read-transfer mode, QSF changes state when a boundary between the two register halves is
reached (see Figure 8 and Figure 9).
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