SMJ44C251B Datasheet, PDF (3/53 Pages) Texas Instruments – 262144 BY 4-BIT MULTIPORT VIDEO RAM

SMJ44C251B
262144 BY 4-BIT
MULTIPORT VIDEO RAM
SGMS058A – MARCH 1995 – REVISED JUNE 1995
description (continued)
Enhanced page-mode operation allows faster memory access by keeping the same row address while selecting
random column addresses. The time for row-address setup, row-address hold, and address multiplex is
eliminated, and a memory cycle time reduction of up to 3× can be achieved, compared to minimum RAS cycle
times. The maximum number of columns that can be accessed is determined by the maximum RAS low time
and page-mode cycle time used. The SMJ44C251B allows a full page (512 cycles) of information to be
accessed in read, write, or read-modify-write mode during a single RAS-low period using relatively conservative
page-mode cycle times.
The SMJ44C251B employs state-of-the-art technology for very high performance combined with improved
reliability. For surface mount technology, the SMJ44C251B is offered in a 28-pin J-leaded chip carrier package
(HJ suffix) or a 28-pin leadless ceramic chip carrier package (HM suffix). The SMJ44C251B is offered in a 28-pin
400-mil dual-in-line ceramic sidebrazed package (JD suffix) or a 28-pin ZIP ceramic package (SV suffix) for
through-hole insertion. The L suffix device is rated for operation from 0°C to 70°C. The M suffix device is rated
for operation from – 55°C to 125°C.
The SMJ44C251B and other multiport video RAMs are supported by a broad line of video/graphic processors
from Texas Instruments, including the SMJ34010 and the SMJ34020 graphics processors.
functional block diagram
DQ0
DQ1
DQ2
DQ3
DSF
SDQ0
SDQ1
SDQ2
SDQ3
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pf
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Write-
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MUX Per-Bit
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Control
Column Decoder
Sense Amplifier
CB
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B
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W/B
Unlatch
W/B
Latch
Address
Mask
D
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Rc
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VCC
VSS
A0
A1
A2
A3
A4
A5
A6
A7
A8
S OB
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a ue
l tr
SB
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rnf
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QSF
Data Transfer
Gate
ÉÉÉÉÉ Serial Data
Register
ÉÉÉÉÉÉÉÉÉÉ Serial Data
Pointer
S
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A
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C
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Split Register
RC
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hr
G
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m
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RAS
CAS
TRG
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SE
• POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443
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