SMJ44C251B Datasheet, PDF (10/53 Pages) Texas Instruments – 262144 BY 4-BIT MULTIPORT VIDEO RAM

SMJ44C251B
262144 BY 4-BIT
MULTIPORT VIDEO RAM
SGMS058A – MARCH 1995 – REVISED JUNE 1995
persistent write-per-bit (continued)
Nonpersistant Write-Per-Bit
RAS
Write-Mask-Register Load
Persistent Write-Per-Bit
CAS
A0 – A8
DSF
W
DQ0 –
DQ3
DQ Mask
Write Data
DQ Mask
Write Data
DQ Mask = H: Write to I/O enabled
= L: Write to I/O disabled
Figure 1. Example of Write-Per-Bit Operations
block write
The block-write mode allows data (present in an on-chip color register) to be written into four consecutive
column-address locations. The 4-bit color register is loaded by the color-register-load cycle. Both write-per-bit
modes can be applied in the block-write cycle. The block-write mode also offers the 4 × 4 column-mask
capability.
load color register
The load-color-register cycle is performed using normal DRAM write-cycle timing except that DSF is held high
on the falling edges of RAS and CAS. A 4-bit code is input to the color register via the random I/O terminals and
latched on the later of the falling edge of CAS or W. After the color register is loaded, it retains data until power
is lost or until another load-color-register cycle is executed.
block write cycle
After the color register is loaded, the block-write cycle can begin as a normal DRAM write cycle with DSF held
high on the falling edge of CAS (see Figures 2, 3, and 4). When the block-write cycle is invoked, each data bit
in the 4-bit color register is written to selected bits of the four adjacent columns of the corresponding random
I/O.
During block-write cycles, only the seven most significant column addresses (A2 – A8) are latched on the falling
edge of CAS. The two least significant addresses (A0 – A1) are replaced by four DQ bits (DQ0 –DQ3), which
are also latched on the later of the falling edge of CAS or W. These four bits are used as a column mask, and
they indicate which of the four column-address locations addressed by A2 – A8 are written with the contents of
the color register during the block-write cycle. DQ0 enables a write to column-address A1 = 0 (low), A0 = 0 (low);
DQ1 enables a write to column-address A1 = 0 (low), A0 = 1 (high); DQ2 enables a write to column-address
A1 = 1 (high), A0 = 0 (low); DQ3 enables a write to column-address A1 = 1 (high), A0 = 1 (high). A high logic
level enables a write, and a low logic level disables the write. A maximum of 16 bits (4 × 4) can be written to
memory during each CAS cycle in the block-write mode.
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