SMJ44C251B Datasheet, PDF (1/53 Pages) Texas Instruments – 262144 BY 4-BIT MULTIPORT VIDEO RAM

D Military Operating Temperature Range
– 55°C to 125°C
D Performance Ranges:
ACCESS ACCESS ACCESS ACCESS
TIME
TIME TIME
TIME
ROW COLUMN SERIAL SERIAL
ADDRESS ENABLE DATA ENABLE
(MAX)
(MAX) (MAX)
(MAX)
ta(R)
’44C251B-10 100 ns
ta(C)
25 ns
ta(SQ)
30 ns
ta(SE)
20 ns
’44C251B-12 120 ns
30 ns 35 ns
25 ns
D Class B High-Reliability Processing
D DRAM: 262 144 Words × 4 Bits
SAM: 512 Words × 4 Bits
D Single 5-V Power Supply (±10% Tolerance)
D Dual Port Accessibility – Simultaneous and
Asynchronous Access From the DRAM and
SAM Ports
D Bidirectional-Data-Transfer Function
Between the DRAM and the Serial-Data
Register
D 4 × 4 Block-Write Feature for Fast Area Fill
Operations; As Many as Four Memory
Address Locations Written per Cycle From
an On-Chip Color Register
D Write-Per-Bit Feature for Selective Write to
Each RAM I/O; Two Write-Per-Bit Modes to
Simplify System Design
description
The SMJ44C251B multiport video RAM is a
high-speed, dual-ported memory device. It
consists of a dynamic random-access memory
(DRAM) organized as 262 144 words of 4 bits
each interfaced to a serial-data register or
serial-access memory (SAM) organized as 512
words of 4 bits each. The SMJ44C251B supports
three types of operation: random access to and
from the DRAM, serial access to and from the
serial register, and bidirectional transfer of data
between any row in the DRAM and the serial
register. Except during transfer operations, the
SMJ44C251B can be accessed simultaneously
and asynchronously from the DRAM and SAM
ports.
SMJ44C251B
262144 BY 4-BIT
MULTIPORT VIDEO RAM
SGMS058A – MARCH 1995 – REVISED JUNE 1995
D Enhanced Page-Mode Operation for Faster
Access
D CAS-Before-RAS (CBR) and Hidden
Refresh Modes
D All Inputs / Outputs and Clocks Are TTL
Compatible
D Long Refresh Period
Every 8 ms (Max)
D Up to 33-MHz Uninterrupted Serial-Data
Streams
D 3-State Serial I/Os Allow Easy Multiplexing
of Video-Data Streams
D 512 Selectable Serial-Register Starting
Locations
D Packaging:
– 28-Pin J-Leaded Ceramic Chip Carrier
Package (HJ Suffix)
– 28-Pin Leadless Ceramic Chip Carrier
Package (HM Suffix)
– 28-Pin Ceramic Sidebrazed DIP
(JD Suffix)
– 28-Pin Zig-Zag In-Line (ZIP), Ceramic
Package (SV Suffix)
D Split Serial-Data Register for Simplified
Real-Time Register Reload
A0 – A8
CAS
DQ0 – DQ3
SE
RAS
SC
SDQ0 – SDQ3
TRG
W
DSF
QSF
VCC
VSS
GND
PIN NOMENCLATURE
Address Inputs
Column Enable
DRAM Data In-Out / Write-Mask Bit
Serial Enable
Row Enable
Serial Data Clock
Serial Data In-Out
Transfer Register / Q Output Enable
Write-Mask Select / Write Enable
Special Function Select
Split-Register Activity Status
5-V Supply
Ground
Ground (Important: Not connected
to internal VSS)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright © 1995, Texas Instruments Incorporated
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