SMJ44C251B Datasheet, PDF (4/53 Pages) Texas Instruments – 262144 BY 4-BIT MULTIPORT VIDEO RAM

SMJ44C251B
262144 BY 4-BIT
MULTIPORT VIDEO RAM
SGMS058A – MARCH 1995 – REVISED JUNE 1995
Function Table
FUNCTION
CBR refresh
Register-to-memory transfer
(transfer write)
Alternate transfer write
(independent of SE)
Serial-write-mode enable
(pseudo-transfer write)
Memory-to-register transfer
(transfer read)
Split-register-transfer read
(must reload tap)
Load and use write mask,
Write data to DRAM
Load and use write mask,
Block write to DRAM
Persistent write-per-bit,
Write data to DRAM
Persistent write-per-bit,
Block write to DRAM
Normal DRAM read/write
(nonmasked)
Block write to DRAM
(nonmasked)
Load write mask
RAS FALL
CAS
FALL
CAS TRG W^‡ DSF SE DSF
L
X
X
X
X
X
H
L
L
X
L
X
H
L
L
H
X
X
H
L
L
L
H
X
H
L
H
L
X
X
H
L
H
H
X
X
H
H
L
L
X
L
H
H
L
L
X
H
H
H
L
H
X
L
H
H
L
H
X
H
H
H
H
L
X
L
H
H
H
L
X
H
H
H
H
H
X
L
Load color register
H
H
H
H
X
H
Legend:
H = High
L = Low
X = Don’t care
† _{R = random access operation; T = transfer operation}
‡ _{In persistent write-per-bit function, W must be high during the refresh cycle.}
§ _{DQ0 – DQ3 are latched on the later of W or CAS falling edge.}
Col Mask = H: Write to address/column location enabled
DQ Mask = H: Write to I/O enabled
ADDRESS
RAS
X
Row
Addr
Row
Addr
Refresh
Addr
Row
Addr
Row
Addr
Row
Addr
Row
Addr
Row
Addr
Row
Addr
Row
Addr
Row
Addr
Refresh
Addr
Refresh
Addr
CAS
X
Tap
Point
Tap
Point
Tap
Point
Tap
Point
Tap
Point
Col
Addr
Blk Addr
A2 – A8
Col
Addr
Blk Addr
A2 – A8
Col
Addr
Blk Addr
A2 – A8
X
X
DQ0 – DQ3
RAS
X
CAS^§
W
X
X
X
X
X
X
X
X
X
X
DQ
Mask
DQ
Mask
X
X
X
X
X
X
X
Valid
Data
Col
Mask
Valid
Data
Col
Mask
Valid
Data
Col
Mask
DQ
Mask
Color
Data
TYPE†
R
T
T
T
T
T
R
R
R
R
R
R
R
R
4
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