SMJ44C251B Datasheet, PDF (29/53 Pages) Texas Instruments – 262144 BY 4-BIT MULTIPORT VIDEO RAM

RAS
CAS
tsu(RA)
A0 – A8
SMJ44C251B
262144 BY 4-BIT
MULTIPORT VIDEO RAM
SGMS058A – MARCH 1995 – REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
tw(RL)P
tw(RH)
td(RLCL)
td(CHRL)
td(RLCA)
tsu(CA)
th(RA)
td(RLCH)
th(RLCA)
tw(CL)
tc(rdWP)
tw(CH)
td(CLRH)
td(CHRL)
th(CLCA)
ta(CP)
td(CARH)
Row
Column
Column
td(CLGH)
DSF
Don’t Care
TRG
tsu( _TRG)
th( _TRG)
tw( _TRG)
tsu( _WMR)
tsu(rd)
td(CLGH)
tdis(G)
td(GLRH)
tw( _TRG)
th(RHrd)
th(CHrd)
W
td(DGL)
DQ0 –
DQ3
Data In
ta(R)‡
ta(CA)
ta(G)
ta(C)
tdis(CH)
Valid Output
ta(G)
ta(CA)†
ta(CP)†
Valid
Output
tdis(G)
tdis(CH)‡
td(DCL)
† _{Access time is ta(CP) or ta(CA) dependent.}
‡ _{Output can go from the high-impedance state to an invalid data state prior to the specified access time.}
NOTE A: A write cycle or a read-modify-write cycle can be mixed with the read cycles as long as the write and read-modify-write timing
specifications are not violated and the proper polarity of DSF is selected on the falling edges of RAS and CAS to select the desired write
mode (normal, block write, etc.)
Figure 17. Enhanced-Page-Mode Read-Cycle Timing
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