SMJ44C251B Datasheet, PDF (14/53 Pages) Texas Instruments – 262144 BY 4-BIT MULTIPORT VIDEO RAM

SMJ44C251B
262144 BY 4-BIT
MULTIPORT VIDEO RAM
SGMS058A – MARCH 1995 – REVISED JUNE 1995
normal-write transfer (SAM-to-DRAM transfer) (continued)
RAS
CAS
A0 – A8
Row
Tap Point
TRG
W
SE
td(SCRL)
SC
td(RHSC)
Figure 6. Normal-Write-Transfer-Cycle Timing
alternate-write transfer (refer to Figure 30)
When DSF is brought high and latched at the falling edge of RAS in the normal-write-transfer cycle, the
alternate-write transfer occurs.
pseudo-write transfer (write-mode control) (refer to Figure 28)
To invoke the pseudo-write transfer (write-mode control cycle), SE is brought high and latched at the falling edge
of RAS. The pseudo-write transfer does not actually invoke any data transfer but switches the mode of the serial
port from the serial-out (read) mode to the serial-in (write) mode.
Before serial data can be clocked into the serial port via the SDQ terminals and the SC input, the SDQ terminals
must be switched into input mode. Because the transfer does not occur during the pseudo-transfer write, the
row address (A0 – A8) is in the don’t care state and the column address (A0 – A8), which is latched on the falling
edge of CAS, selects one of the 512 tap points in the SAM that are available for the next serial input.
read transfer (DRAM-to-SAM transfer) (refer to Figure 7)
During a read-transfer cycle, data from the selected row in DRAM is transferred to SAM. There are two
read-transfer operations: normal-read transfer and split-register-read transfer.
normal-read transfer (refer to Figure 7)
The normal-read-transfer operation loads data from a selected row in DRAM into SAM. TRG is brought low and
latched at the falling edge of RAS. Nine row-address bits (A0 – A8) are also latched at the falling edge of RAS
to select one of the 512 rows available for transfer. The nine column-address bits (A0 – A8) are latched at the
falling edge of CAS to select one of the SAM’s 512 available tap points where the serial data is read out.
A normal-read transfer can be performed in three ways: early-load read transfer, real-time or midline-load read
transfer, and late-load read transfer. Each of these offers the flexibility of controlling the TRG trailing edge in
the read-transfer cycle (see Figure 7).
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