SMJ44C251B Datasheet, PDF (36/53 Pages) Texas Instruments – 262144 BY 4-BIT MULTIPORT VIDEO RAM

SMJ44C251B
262144 BY 4-BIT
MULTIPORT VIDEO RAM
SGMS058A – MARCH 1995 – REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
tw(RL)P
RAS
CAS
A0 – A8
DSF
TRG
th(RA)
th(SFR)
td(RLCH)
td(RLCL)
td(CHRL)
tw(CH)
tw(CL)
tc(P)
td(CLRH)
td(CHRL)
td(RLCA)
tsu(CA)
tsu(RA)
Row
th(RLCA)
Block Address
A2 – A8
th(CLCA)
td(CARH)
Block Address
A2 – A8
tsu(SFR)
1
th( _TRG)
tsu( _TRG)
th(SFC)
tsu(SFC)
th(SFC)
tsu(SFC)
See Note A
tw(RH)
th(RWM)
tsu( _WMR)
tsu( _WCH)
tw( _WL)
tsu( _WCH)
tsu( _WRH)
W
2
tsu(DWL)†
tsu(DQR)
th(RDQ)
th(CLD)†
th( _WLD)†
tsu(DCL)†
th(RLD)
DQ0 – DQ3
3
4
4
† _{Referenced to CAS or W, whichever occurs last}
NOTE A: TRG must remain high throughout the entire page-mode operation to assure page-mode cycle time if the late write feature is used. If
the early-write-cycle timing is used, the state of TRG is a don’t care after the minimum period th( _TRG) from the falling edge of RAS.
Figure 24. Enhanced-Page-Mode Block-Write-Cycle Timing
Table 11. Enhanced-Page-Mode Block-Write-Cycle Table
CYCLE
Write-mask load/use, block write
Use previous write mask, block write
Write mask disabled, block write to all I/Os
Write mask data 0: I/O write disable
1: I/O write enable
Column mask data DQn =
0 column write disable
(n = 0, 1, 2, 3) 1 column write enable
STATE
1
2
3
4
L
L
Write mask Column mask
H
L
Don’t care Column mask
L
H
Don’t care Column mask
DQ0 — column 0 (address A1 = 0, A0 = 0)
DQ1 — column 1 (address A1 = 0, A0 = 1)
DQ2 — column 2 (address A1 = 1, A0 = 0)
DQ3 — column 3 (address A1 = 1, A0 = 1)
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