SMJ44C251B Datasheet, PDF (44/53 Pages) Texas Instruments – 262144 BY 4-BIT MULTIPORT VIDEO RAM

SMJ44C251B
262144 BY 4-BIT
MULTIPORT VIDEO RAM
SGMS058A – MARCH 1995 – REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
RAS
CAS
A0 – A8
td(CHRL)
tw(RL)
td(RLCL)
tc( _TRD)
td(RLCH)
tw(CL)
tsu(RA)
th(RA)
tsu(SFR)
Row
td(RLCA)
th(RLCA)
tsu(CA)
th(CLCA)
Tap Point
th(SFR) _{A0 – A8}
tw(RH)
Don’t Care
DSF
TRG
tsu( _TRG)
td(CLGH)
td(CAGH)
td(RLTH)
Don’t Care
td( _THRL)
td( _THRH)
tsu( _WMR)
W
th(RWM)
tw(GH)
Don’t Care
DQ0 – DQ3
tw(SCH)
td(SCTR)
Hi-Z
td( _THSC)
SC
th(SHSQ)
ta(SQ)
tw(SCL)
th(SHSQ)
ta(SQ)
tc(SC)
SDQ0 – SDQ3
Old Data
Old Data
Old Data
New Data
td(GHQSF)
QSF
Tap Point Bit A7
H
SE
L
td(CLQSF)
td(RLQSF)
NOTES: A. Late-load operation is defined as td( _THRH) < 0 ns.
B. DQ outputs remain in the high-impedance state for the entire memory-to-data-register transfer cycle. The memory-to-data-register
transfer cycle is used to load the data registers in parallel from the memory array. The 512 locations in each data register are written
from the 512 corresponding columns of the selected row. The data that is transferred into the data registers can be either shifted
out or transferred back into another row.
C. Once data is transferred into the data registers, the SAM is in the serial read mode (i.e., SQ is enabled), allowing data to be shifted
out of the registers. Also, the first bit to be read from the data register after TRG has gone high must be activated by a positive
transition of SC.
Figure 32. Memory-to-Data-Register Transfer-Cycle Timing,
Real-Time-Reload Operation/Late-Load Operation
44
• POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443