SMJ44C251B Datasheet, PDF (24/53 Pages) Texas Instruments – 262144 BY 4-BIT MULTIPORT VIDEO RAM

SMJ44C251B
262144 BY 4-BIT
MULTIPORT VIDEO RAM
SGMS058A – MARCH 1995 – REVISED JUNE 1995
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (concluded)^†
td(MSRL)
ALT.
SYMBOL
Delay time, last (most significant) rising edge of SC to RAS low before
boundary switch during split-register read-transfer cycles
’44C251B - 10
MIN MAX
25
’44C251B - 12
MIN MAX
25
UNIT
ns
td(SCQSF)
Delay time, last (255 or 511) rising edge of SC to QSF switching at the
boundary during split-register read-transfer cycles (see Note 7)
tSQD
40
40 ns
td(CLQSF)
Delay time, CAS low to QSF switching in read-transfer or write-transfer
cycles (see Note 7)
tCQD
35
35 ns
td(GHQSF)
Delay time, TRG high to QSF switching in read-transfer or write-transfer
cycles (see Note 7)
tTQD
30
30 ns
td(RLQSF)
Delay time, RAS low to QSF switching in read-transfer or write-transfer
cycles (see Note 7)
tRQD
75
75 ns
trf
Refresh time interval, memory
tREF
tt
Transition time
tT
† _{Timing measurements are referenced to VIL max and VIH min.}
NOTE 7: Switching times assume CL = 100 pF unless otherwise noted (see Figure 12).
8
3
50
8 ms
3
50 ns
PARAMETER MEASUREMENT INFORMATION
1.31 V
Output
Pin
218 Ω
CL
VSS
Figure 12. Load Circuit
24
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