SMJ44C251B Datasheet, PDF (12/53 Pages) Texas Instruments – 262144 BY 4-BIT MULTIPORT VIDEO RAM

SMJ44C251B
262144 BY 4-BIT
MULTIPORT VIDEO RAM
SGMS058A – MARCH 1995 – REVISED JUNE 1995
block write cycle (continued)
DQ MASK
DQ0
1
DQ1
1
DQ2
0
DQ3
1
COLUMN
MASK
0
1
1
1
COLOR
REGISTER
DATA
0
0
1
1
Block Write
COLUMN 1 COLUMN 2 COLUMN 3 COLUMN 4
DQ0
DQ1
DQ2
DQ3
Masked
Masked
Masked
Masked
0
0
Masked
1
0
0
Masked
1
0
0
Masked
1
Figure 4. Example of Block Write Operation With DQ Mask and Address Mask
transfer operation
Transfer operations between the memory arrays (DRAM) and the data registers (SAM) are invoked by bringing
TRG low before RAS falls. The states of W, SE, and DSF, which are also latched on the falling edge of RAS,
determine which transfer operation is invoked. Figure 5 shows an overview of data flow between the random
and the serial interfaces.
TRG
A8
DSF
W
SE
Transfer -
Control
Logic
Random-Access Port
Col
Col Col
Col
0
255 256
511
Row
0
Memory Array
262 144 Bits
Row
511
256
256
4
DQ0 – DQ3
Transfer -
Pass
Gate
Transfer -
Pass
Gate
256
256 - Bit Data Register
256
256 - Bit Data Register
SC
A0 – A8
A8
4
SDQ0 – SDQ3
Serial
Counter
MUX
SE
TRG
W
Serial -
I/O
Control
Figure 5. Block Diagram Showing One Random and One Serial-I/O Interface
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