CC2500_06 Datasheet, PDF (47/84 Pages) Texas Instruments – Single Chip Low Cost Low Power RF Transceiver

CC2500
GDOx_CFG[5:0]] Description
0 (0x00)
Associated with the RX FIFO: Asserts when RX FIFO is filled at or above RXFIFO_THR. De-asserts when RX FIFO is
drained below RXFIFO_THR.
1 (0x01)
Associated with the RX FIFO: Asserts when RX FIFO is filled at or above RXFIFO_THR or the end of packet is
reached. De-asserts when RX FIFO is empty.
2 (0x02)
Associated with the TX FIFO: Asserts when the TX FIFO is filled at or above TXFIFO_THR. De-asserts when the TX
FIFO is below TXFIFO_THR.
3 (0x03)
Associated with the TX FIFO: Asserts when TX FIFO is full. De-asserts when the TX FIFO is drained below
TXFIFO_THR.
4 (0x04) Asserts when the RX FIFO has overflowed. De-asserts when the FIFO has been flushed.
5 (0x05) Asserts when the TX FIFO has underflowed. De-asserts when the FIFO is flushed.
6 (0x06)
Asserts when sync word has been sent / received, and de-asserts at the end of the packet. In RX, the pin will de-assert
when the optional address check fails or the RX FIFO overflows. In TX the pin will de-assert if the TX FIFO underflows.
7 (0x07)
Asserts when a packet has been received with CRC OK. De-asserts when the first byte is read from the RX FIFO. Only
valid if PKTCTRL0.CC2400_EN = 1.
8 (0x08) Preamble Quality Reached. Asserts when the PQI is above the programmed PQT value.
9 (0x09) Clear channel assessment. High when RSSI level is below threshold (dependent on the current CCA_MODE setting)
10 (0x0A)
Lock detector output. The PLL is in lock if the lock detector output has a positive transition or is constantly logic high. To
check for PLL lock the lock detector output should be used as an interrupt for the MCU.
11 (0x0B)
Serial Clock. Synchronous to the data in synchronous serial mode.
Data is set up on the falling edge and is read on the rising edge of SERIAL_CLK when GDOx_INV=0.
12 (0x0C)
Serial Synchronous Data Output (DO). Used for synchronous serial mode. The MCU must read DO on the rising edge
of SERIAL_CLK when GDOx_INV=0. Data is set up on the falling edge by CC2500.
13 (0x0D) Serial transparent Data Output. Used for asynchronous serial mode.
14 (0x0E) Carrier sense. High if RSSI level is above threshold.
15 (0x0F)
CRC_OK. The last CRC comparison matched. Cleared when entering/restarting RX mode. Only valid if
PKTCTRL0.CC2400_EN = 1.
16 (0x10) Reserved – used for test.
17 (0x11) Reserved – used for test.
18 (0x12) Reserved – used for test.
19 (0x13) Reserved – used for test.
20 (0x14) Reserved – used for test.
21 (0x15) Reserved – used for test.
22 (0x16) RX_HARD_DATA[1]. Can be used together with RX_SYMBOL_TICK for alternative serial RX output.
23 (0x17) RX_HARD_DATA[0]. Can be used together with RX_SYMBOL_TICK for alternative serial RX output.
24 (0x18) Reserved – used for test.
25 (0x19) Reserved – used for test.
26 (0x1A) Reserved – used for test.
27 (0x1B)
PA_PD. Note: PA_PD will have the same signal level in SLEEP and TX states. To control an external PA or RX/TX
switch in applications where the SLEEP state is used it is recommended to use address 47 (0x2F).
28 (0x1C)
LNA_PD. Note: LNA_PD will have the same signal level in SLEEP and RX states. To control an external LNA or RX/TX
switch in applications where the SLEEP state is used it is recommended to use address 47 (0x2F).
29 (0x1D) RX_SYMBOL_TICK. Can be used together with RX_HARD_DATA for alternative serial RX output.
30 (0x1E) Reserved – used for test.
31 (0x1F) Reserved – used for test.
32 (0x20) Reserved – used for test.
33 (0x21) Reserved – used for test.
34 (0x22) Reserved – used for test.
35 (0x23) Reserved – used for test.
36 (0x24) WOR_EVNT0
37 (0x25) WOR_EVNT1
38 (0x26) Reserved – used for test.
39 (0x27) Reserved – used for test.
40 (0x28) Reserved – used for test.
41 (0x29) CHIP_RDY
42 (0x2A) Reserved – used for test.
43 (0x2B) XOSC_STABLE
44 (0x2C) Reserved – used for test.
45 (0x2D) GDO0_Z_EN_N. When this output is 0, GDO0 is configured as input (for serial TX data).
46 (0x2E) High impedance (3-state)
47 (0x2F) HW to 0 (HW1 achieved with _INV signal). Can be used to control an external LNA/PA or RX/TX switch.
48 (0x30) CLK_XOSC/1
49 (0x31) CLK_XOSC/1.5
50 (0x32) CLK_XOSC/2
51 (0x33) CLK_XOSC/3
52 (0x34) CLK_XOSC/4
53 (0x35) CLK_XOSC/6
54 (0x36) CLK_XOSC/8
Note: There are 3 GDO pins, but only one CLK_XOSC/n can be selected as an output at any
55 (0x37) CLK_XOSC/12
time. If CLK_XOSC/n is to be monitored on one of the GDO pins, the other two GDO pins must
56 (0x38) CLK_XOSC/16
be configured to values less than 0x30. The GDO0 default value is CLK_XOSC/192.
57 (0x39) CLK_XOSC/24
58 (0x3A) CLK_XOSC/32
59 (0x3B) CLK_XOSC/48
60 (0x3C) CLK_XOSC/64
61 (0x3D) CLK_XOSC/96
62 (0x3E) CLK_XOSC/128
63 (0x3F) CLK_XOSC/192
Table 33: GDOx signal selection (x = 0, 1 or 2)
PRELIMINARY Data Sheet (Rev.1.2) SWRS040A
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