CC2500_06 Datasheet, PDF (20/84 Pages) Texas Instruments – Single Chip Low Cost Low Power RF Transceiver

CC2500
t _sp
t _ch
t _cl
t_sd
t_hd
t _ns
SCLK:
CSn:
Write to register:
SI ^X
0
A6 A5 A4 A3 A2 A1 A0 X D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0
W
W
W
W
W
W
W
W
X
SO ^{Hi-Z S7}
S6
S5
S4
S3
S2
S1
S0
S7
S6 S5 S4 S3 S2 S1 S0 S7 Hi-Z
Read from register:
SI ^X
1
A6 A5
A4 A3 A2 A1 A0
X
SO ^{Hi-Z S7}
S6
S5
S4
S3
S2
S1
S0
D7
D6 D 5 D4 D3 D 2 D1
R
R
R
R
R
R
R
D0
R
Hi-Z
Figure 7: Configuration register write and read operations (A6 is the “burst” bit)
Parameter Description
Min
f_SCLK
SCLK frequency
-
100 ns delay inserted between address byte and data byte (single access), or between
address and data, and between each data byte (burst access).
SCLK frequency, single access
No delay between address and data byte
SCLK frequency, burst access
No delay between address and data byte, or between data bytes
t_sp,pd
CSn low to positive edge on SCLK, in power-down mode
200
t_sp
CSn low to positive edge on SCLK, in active mode
20
t_ch
Clock high
50
t_cl
Clock low
50
t_rise
Clock rise time
-
t_fall
Clock fall time
-
t_sd
Setup data (negative SCLK edge) to
Single access
55
positive edge on SCLK
Burst access
76
(t_sd applies between address and data bytes, and
between data bytes)
t_hd
Hold data after positive edge on SCLK
20
t_ns
Negative edge on SCLK to CSn high
20
Table 16: SPI interface timing requirements
Max
Units
10
MHz
9
MHz
6.5
MHz
-
µs
-
ns
-
ns
-
ns
5
ns
5
ns
-
ns
-
ns
-
ns
-
ns
CSn:
Command strobe(s):
Read or write register(s):
Read or write consecutive registers (burst):
Read or write n+1 bytes from/to RF FIFO:
Combinations:
ADDR_strobe ADDR_strobe ADDR_strobe ...
ADDR_reg DATA ADDR_reg DATA ADDR_reg DATA ...
ADDR_{reg n} DATA_n DATA_n+1 DATA_n+2
...
ADDR_FIFO DATA_{byte 0} DATA_{byte 1} DATA_{byte 2}
...
DATA_{byte n-1} DATA_{byte n}
ADDR_reg DATA ADDR_strobe ADDR_reg DATA ADDR_strobe ADDR_FIFO DATA_{byte 0} DATA_{byte 1} ...
Figure 8: Register access types
PRELIMINARY Data Sheet (Rev.1.2) SWRS040A
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