CC2500_06 Datasheet, PDF (46/84 Pages) Texas Instruments – Single Chip Low Cost Low Power RF Transceiver

CC2500
26.1 Reference Signal
The chip can alternatively be operated with a
reference signal from 26 to 27 MHz instead of
a crystal. This input clock can either be a full-
swing digital signal (0 V to VDD) or a sine
wave of maximum 1 V peak-peak amplitude.
The reference signal must be connected to the
XOSC_Q1 input. The sine wave must be
connected to XOSC_Q1 using a serial
capacitor. The XOSC_Q2 line must be left un-
connected. C81 and C101 can be omitted
when using a reference signal.
27 External RF Match
The balanced RF input and output of CC2500
share two common pins and are designed for
a simple, low-cost matching and balun network
on the printed circuit board. The receive- and
transmit switching at the CC2500 front-end is
controlled by a dedicated on-chip function,
eliminating the need for an external RX/TX-
switch.
A few passive external components combined
with the internal RX/TX switch/termination
circuitry ensures match in both RX and TX
mode.
Although CC2500 has a balanced RF
input/output, the chip can be connected to a
single-ended antenna with few external low
cost capacitors and inductors.
The passive matching/filtering network
connected to CC2500 should have the following
differential impedance as seen from the RF-
port (RF_P and RF_N) towards the antenna:
Z_out = 80 + j74 Ω
To ensure optimal matching of the CC2500
differential output it is highly recommended to
follow the CC2500EM reference designs as
closely as possible. Gerber files for the
reference designs are available for download
from the TI and Chipcon websites.
28 General Purpose / Test Output Control Pins
The three digital output pins GDO0, GDO1 and
GDO2 are general control pins configured with
IOCFG0.GDO0_CFG, IOCFG1.GDO1_CFG
and IOCFG2.GDO3_CFG respectively. Table
33 shows the different signals that can be
monitored on the GDO pins. These signals can
be used as an interrupt to the MCU. GDO1 is
the same pin as the SO pin on the SPI
interface, thus the output programmed on this
pin will only be valid when CSn is high. The
default value for GDO1 is 3-stated, which is
useful when the SPI interface is shared with
other devices.
The default value for GDO0 is a 135-141 kHz
clock output (XOSC frequency divided by 192).
Since the XOSC is turned on at power-on-
reset, this can be used to clock the MCU in
systems with only one crystal. When the MCU
is up and running, it can change the clock
frequency by writing to IOCFG0.GDO0_CFG.
An on-chip analog temperature sensor is
enabled by writing the value 128 (0x80h) to the
IOCFG0.GDO0_CFG register. The voltage on
the GDO0 pin is then proportional to
temperature. See Section 4.7 on page 12 for
temperature sensor specifications.
PRELIMINARY Data Sheet (Rev.1.2) SWRS040A
Page 46 of 83