CC2500_06 Datasheet, PDF (30/84 Pages) Texas Instruments – Single Chip Low Cost Low Power RF Transceiver

CC2500
length is enabled. The length byte has a value
equal to the payload of the packet (including
the optional address byte). If fixed packet
length is enabled, then the first byte written to
the TX FIFO is interpreted as the destination
address, if this feature is enabled in the device
that receives the packet.
The modulator will first send the programmed
number of preamble bytes. If data is available
in the TX FIFO, the modulator will send the
two-byte (optionally 4-byte) sync word and
then the payload in the TX FIFO. If CRC is
enabled, the checksum is calculated over all
the data pulled from the TX FIFO and the
result is sent as two extra bytes at the end of
the payload data.
If whitening is enabled, the length byte,
payload data and the two CRC bytes will be
whitened. This is done before the optional
FEC/Interleaver stage. Whitening is enabled
by setting PKTCTRL0.WHITE_DATA=1.
If FEC/Interleaving is enabled, the length byte,
payload data and the two CRC bytes will be
scrambled by the interleaver, and FEC
encoded before being modulated.
15.6 Packet Handling in Receive Mode
In receive mode, the demodulator and packet
handler will search for a valid preamble and
the sync word. When found, the demodulator
has obtained both bit and byte synchronism
and will receive the first payload byte.
If FEC/Interleaving is enabled, the FEC
decoder will start to decode the first payload
byte. The interleaver will de-scramble the bits
before any other processing is done to the
data.
If whitening is enabled, the data will be de-
whitened at this stage.
When variable packet length is enabled, the
first byte is the length byte. The packet handler
stores this value as the packet length and
receives the number of bytes indicated by the
length byte. If fixed packet length is used, the
packet handler will accept the programmed
number of bytes.
Next, the packet handler optionally checks the
address and only continues the reception if the
address matches. If automatic CRC check is
enabled, the packet handler computes CRC
and matches it with the appended CRC
checksum.
At the end of the payload, the packet handler
will optionally write two extra packet status
bytes that contain CRC status, link quality
indication and RSSI value.
16 Modulation Formats
CC2500 supports amplitude, frequency and
phase shift modulation formats. The desired
modulation format is set in the
MDMCFG2.MOD_FORMAT register.
Optionally, the data stream can be Manchester
coded by the modulator and decoded by the
demodulator. This option is enabled by setting
MDMCFG2.MANCHESTER_EN=1. Manchester
encoding is not supported at the same time as
using the FEC/Interleaver option.
16.1 Frequency Shift Keying
FSK can optionally be shaped by a Gaussian
filter with BT=1, producing a GFSK modulated
signal.
The frequency deviation is programmed with
the DEVIATION_M and DEVIATION_E values
in the DEVIATN register. The value has an
exponent/mantissa form, and the resultant
deviation is given by:
f _dev
=
f _xosc
2¹⁷
⋅ (8 + DEVIATION _ M ) ⋅ 2^{DEVIATION _ E}
The symbol encoding is shown in Table 23.
Format
FSK\GFSK
Symbol
‘0’
‘1’
Coding
– Deviation
+ Deviation
Table 23: Symbol encoding for FSK
modulation
16.2 Minimum Shift Keying
When using MSK¹, the complete transmission
(preamble, sync word and payload) will be
MSK modulated.
1 _{Identical to offset QPSK with half-sine}
shaping (data coding may differ)
PRELIMINARY Data Sheet (Rev.1.2) SWRS040A
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