CC2500_06 Datasheet, PDF (25/84 Pages) Texas Instruments – Single Chip Low Cost Low Power RF Transceiver

CC2500
MDMCFG4.
CHANBW_M
00
01
10
11
MDMCFG4.CHANBW_E
00 01 10 11
812 406 203 102
650 325 162 81
541 270 135 68
464 232 116 58
Table 20: Channel filter bandwidths [kHz]
(assuming a 26 MHz crystal)
For best performance, the channel filter
bandwidth should be selected so that the
signal bandwidth occupies at most 80% of the
channel filter bandwidth. The channel centre
tolerance due to crystal accuracy should also
be subtracted from the signal bandwidth. The
following example illustrates this:
With the channel filter bandwidth set to 600
kHz, the signal should stay within 80% of 600
kHz, which is 480 kHz. Assuming 2.44 GHz
frequency and ±20 ppm frequency uncertainty
for both the transmitting device and the
receiving device, the total frequency
uncertainty is ±40 ppm of 2.44 GHz, which is
±98 kHz. If the whole transmitted signal
bandwidth is to be received within 480 kHz,
the transmitted signal bandwidth should be
maximum 480 kHz – 2·98 kHz, which is 284
kHz.
14 Demodulator, Symbol Synchronizer and Data Decision
CC2500 contains an advanced and highly
configurable demodulator. Channel filtering
and frequency offset compensation is
performed digitally. To generate the RSSI level
(see Section 17.3 for more information) the
signal level in the channel is estimated. Data
filtering is also included for enhanced
performance.
14.1 Frequency Offset Compensation
When using FSK, GFSK or MSK modulation,
the demodulator will compensate for the offset
between the transmitter and receiver
frequency, within certain limits, by estimating
the centre of the received data. This value is
available in the FREQEST status register.
Writing the value from FREQEST into
FSCTRL0.FREQOFF
the
frequency
synthesizer is automatically adjusted
according to the estimated frequency offset.
Note that frequency offset compensation is not
supported for OOK modulation.
14.2 Bit Synchronization
The bit synchronization algorithm extracts the
clock from the incoming symbols. The
algorithm requires that the expected data rate
is programmed as described in Section 12 on
page 24. Re-synchronization is performed
continuously to adjust for error in the incoming
symbol rate.
14.3 Byte Synchronization
Byte synchronization is achieved by a
continuous sync word search. The sync word
is a 16 or 32 bit configurable field that is
automatically inserted at the start of the packet
by the modulator in transmit mode. The
demodulator uses this field to find the byte
boundaries in the stream of bits. The sync
word will also function as a system identifier,
since only packets with the correct predefined
sync word will be received. The sync word
detector correlates against the user-configured
16-bit sync word. The correlation threshold
can be set to 15/16 bits match or 16/16 bits
match. The sync word can be further qualified
using the preamble quality indicator
mechanism described below and/or a carrier
sense condition. The sync word is
programmed with SYNC1 and SYNC0.
In order to make false detections of sync
words less likely, a mechanism called
preamble quality indication (PQI) can be used
to qualify the sync word. A threshold value for
the preamble quality must be exceeded in
order for a detected sync word to be accepted.
See Section 17.2 on page 31 for more details.
PRELIMINARY Data Sheet (Rev.1.2) SWRS040A
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