CC2500_06 Datasheet, PDF (24/84 Pages) Texas Instruments – Single Chip Low Cost Low Power RF Transceiver

internally according to the control coding. It is
only possible to change state with this
functionality. That means that for instance RX
will not be restarted if SI and SCLK are set to
RX and CSn toggles. When CSn is low the SI
and SCLK has normal SPI functionality.
All pin control command strobes are executed
immediately, except the SPWD strobe, which is
delayed until CSn goes high.
CC2500
CSn
1
↓
↓
↓
↓
0
SCLK
X
0
0
1
1
SPI
mode
SI
X
0
1
0
1
SPI
mode
Function
Chip unaffected by
SCLK/SI
Generates SPWD strobe
Generates STX strobe
Generates SIDLE strobe
Generates SRX strobe
SPI mode (wakes up into
IDLE if in SLEEP/XOFF)
Table 18: Optional pin control coding
12 Data Rate Programming
The data rate used when transmitting, or the
data rate expected in receive is programmed
by the MDMCFG3.DRATE_M and the
MDMCFG4.DRATE_E configuration registers.
The data rate is given by the formula below.
As the formula shows, the programmed data
rate depends on the crystal frequency.
( ) _{RDATA =}
256 + DRATE _ M
2²⁸
⋅ 2^{DRATE _ E} _{⋅ f XOSC}
The following approach can be used to find
suitable values for a given data rate:
DRATE
_
E
=
⎢
⎢^log
⎢⎣
2
⎜⎜⎝⎛
R_DATA ⋅ 2 ²⁰
f _XOSC
⎟⎟⎠⎞⎥⎥⎦⎥
DRATE _ M = ^{RDATA ⋅ 228} − 256
f _XOSC ⋅ 2 ^{DRATE _ E}
If DRATE_M is rounded to the nearest integer
and becomes 256, increment DRATE_E and
use DRATE_M=0.
The data rate can be set from 1.2 kbps to 500
kbps with the minimum step size of:
Data rate
start
[kbps]
0.8
3.17
6.35
12.7
25.4
50.8
101.6
203.1
406.3
Typical
data rate
[kbps]
1.2/2.4
4.8
9.6
19.6
38.4
76.8
153.6
250
500
Data rate
stop [kbps]
3.17
6.35
12.7
25.4
50.8
101.6
203.1
406.3
500
Data rate
step size
[kbps]
0.0062
0.0124
0.0248
0.0496
0.0992
0.1984
0.3967
0.7935
1.5869
Table 19: Data rate step size
13 Receiver Channel Filter Bandwidth
In order to meet different channel width
requirements, the receiver channel filter is
programmable. The MDMCFG4.CHANBW_E and
MDMCFG4.CHANBW_M configuration registers
control the receiver channel filter bandwidth,
which scales with the crystal oscillator
frequency. The following formula gives the
relation between the register settings and the
channel filter bandwidth:
BW_channel
=
f _XOSC
8 ⋅ (4 + CHANBW _ M )·2^{CHANBW_ E}
The CC2500 supports the following channel
filter bandwidths:
PRELIMINARY Data Sheet (Rev.1.2) SWRS040A
Page 24 of 83