SLWS132 Datasheet, PDF (43/46 Pages) Texas Instruments – QUAD RECEIVER CHIP

GC4014 QUAD RECEIVER CHIP
7.8 OUTPUT TEST CONFIGURATION
DATA SHEET REV 0.6
The following configuration allows the user to debug the output interface to insure that the GC4014 data is
being received properly by the following circuitry. The configuration in the following table will generate a fixed output
sequence of four values (two complex pairs) which will repeat indefinitely:
Table 17: Output Test Configuration
Control Registers
Channel pages 4,5,6,7
Address
Data
Address
Data
00 (HEX)
6A (HEX)¹
10 (HEX)
00 (HEX)
01
81
11
00
02
0F²
12
00
03
00²
13
00
04
63²
14
00
05
00
15
00
06
11³
16
80
07
10
17
74
08
50
18
FF
09
AA
19
0A
FF
1A
0B
FF
1B
0C
0F
1C
0D
0P⁴
1D
0E
00
1E
0F
read only
1F
1. Initialize to 6A while configuring the chip(s), then set to EA, then back to 6A to fire off the one-shot sync.
2. Gives an overall decimate by 64, See Table 18 for other values.
3. Value is application dependent.
4. “P” is the page number. The upper nibble should stay at “0¨.
The programmable PFIR coefficients are not used and do not need to be loaded. The user should change
address 6 (Output Format Register) to reflect the desired serial or link output mode. The expected results for various
decimation ratios are shown below:
Table 18: Test Output Sequence
Decimation Controls
Overall
Decimation
32
64
128
256
512
1024
2048
100
Addresses
2, 3
07, 00
0F, 00
1F, 00
3F, 00
7F, 00
FF, 00
FF, 01
18, 00
Address 4
71
63
55
51
43
35
31
60
I₀
8000
8000
Output Sequence
Q₀
FD00
I₁
7F00
Q₁
0300
FE00
7F00
0200
The output sequence is the same for all power-of-two decimations. Other decimation ratios, with the SCALE
and BIG_SCALE values being the maximum which satisfy: (SCALE + 6 × BIG_SCALE) ≤ (56 – 4log₂N) , will result in
sequences with the same I values, but with slightly different Q values.
GRAYCHIP, INC.
- 38 -
APRIL 27, 1999
This document contains information which may be changed at any time without notice