SLWS132 Datasheet, PDF (23/46 Pages) Texas Instruments – QUAD RECEIVER CHIP

GC4014 QUAD RECEIVER CHIP
DATA SHEET REV 0.6
5.2 DECIMATION MODE REGISTER
Registers 1 and 2 control the decimation modes for the chip. These settings are common to all channels
ADDRESS 1:
BIT
0 LSB
TYPE
R/W
1
R/W
2
R/W
3
R/W
4
R/W
5
R/W
6
R/W
7 MSB
R/W
Decimation Mode, suggested default = 0x80, power up resets to 0.
NAME
REAL
FILTER_SELECT
RDY_POL
RDY_WIDTH
LINK_MODE
SO_INT_MODE
NO_SYMMETRY
EN_DOUBLER
DESCRIPTION
Enables the PFIR’s real output mode. (See Section 3.3.6). The real outputs are formatted
into complex pairs in the real mode. The I-output words contain are the even-time real
outputs and the Q-outputs contain the odd-time real outputs.
The user downloaded filter coefficients are used instead of the built in filter coefficients for
the second stage FIR filter when this bit is set.
This control bit inverts the polarity of the RDY output. Normally RDY pulses high when a new
sample is ready and an output sample period (OSP) is starting. RDY will pulse low when
RDY_POL is high.
Normally the RDY pin will pulse active for four clock cycles. This control bit forces RDY to be
active for 16 clocks.
Output the data in the nibble-serial link mode. The RDY/ACK pin becomes an input pin in this
mode. NOTE: To use the link mode this bit must be set before the OUTPUT_ENABLE control
bit in register 8 is set, otherwise the RDY/ACK pin will be driven as an output, possibly
damaging the pin.
The SO output pin is used as an overflow interrupt pin when this bit is set. If an overflow due
to gain settings occurs in any of the channels the SO pin will go low if this bit is set.
The second stage decimate by two filter is normally a 63 tap symmetric filter. It becomes a
32 tap non-symmetric filter when this bit is set. ERRATA: The non-symmetry mode does not
work properly for parts marked with mask code 55532B, parts with other mask codes work.
Contact GRAYCHIP for details.
This bit must be set to enable the clock doubler circuit when the CKMODE pin is low. This bit
is ignored when CKMODE pin is tied high.
5.3 CIC DECIMATION REGISTERS
Registers 2, and 3 contain the 14 bit CIC decimation ratio control.
ADDRESS 2:
Decimation Byte 0, suggested default = 0x07
BIT
TYPE
0-7
R/W
NAME
DEC[0:7]
DESCRIPTION
The LSBs of the decimation control
ADDRESS 3:
Decimation Byte 1, suggested default = 0x00
BIT
TYPE
NAME
DESCRIPTION
0-5
R/W
6,7
R
DEC[8:13]
zero
The 6 MSBs of the decimation control
These bits are read only zeros.
Where DEC is equal to N-1. The chip decimates the input data by a factor of 2N for real output data and 4N
for complex output data (or 8N if DEC_BY_4 is set in Register 13), where N ranges from 8 to 16384. This provides
an decimation range from 32 to 65,536 for complex output signals and 16 to 32,768 for real output signals.
GRAYCHIP, INC.
- 18 -
APRIL 27, 1999
This document contains information which may be changed at any time without notice