SLWS132 Datasheet, PDF (26/46 Pages) Texas Instruments – QUAD RECEIVER CHIP

GC4014 QUAD RECEIVER CHIP
DATA SHEET REV 0.6
5.9 CHANNEL FLUSH CONTROL REGISTER
This register controls flushing the four channels. Each channel is flushed when the selected sync occurs
The sync is selected according to Table 4 in Section 5.1.
ADDRESS 9:
Channel Flush Register, suggested default = 0x55
BIT
TYPE
NAME
DESCRIPTION
0,1 LSB
R/W
2,3
R/W
4,5
R/W
6,7 MSB
R/W
FLUSH_A[0:1]
FLUSH_B[0:1]
FLUSH_C[0:1]
FLUSH_D[0:1]
The flush sync for channel A.
The flush sync for channel B.
The flush sync for channel C.
The flush sync for channel D.
Each channel should be flushed when the chip is being initialized or when the decimation control is
changed. The flush lasts for 8N clocks after the sync occurs. The channel flush syncs will normally be left in a “never”
mode. If a channel is unused, then the user should leave the channel in the “always” flush mode which will clear the
datapath, clear the channel’s output, and lower its power consumption. During diagnostics the channels will need
to be flushed at the beginning of each sync cycle.
The user may wish to flush a channel when a new frequency is selected in order to purge the datapath of
the last signal.
5.10 COUNTER MODE REGISTERS
Registers 10, and 11 set the counter’s cycle period.
ADDRESS 10: Counter Byte 0, suggested default = 0xff
BIT
TYPE
0-7
R/W
NAME
CNT[0:7]
DESCRIPTION
The LSBs of the counter cycle period
ADDRESS 11: Counter Byte 1, suggested default = 0xff
BIT
TYPE
NAME
DESCRIPTION
0-7
R/W
CNT[8:15]
The 8 MSBs of the counter cycle period
The chip’s internal sync counter counts in cycles of 128(CNT+1) clocks. A terminal count signal (TC) is
output at the end of each cycle. The counter can be synchronized to an external sync as specified in the Sync mode
Register (See Section 5.1). If CNT is set so that 128(CNT+1) is a multiple of twice the decimation ratio (i.e., a
multiple of 16N), then the terminal count of this counter can be output on the SO pin and used to periodically
synchronize multiple GC4014 chips.
GRAYCHIP, INC.
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APRIL 27, 1999
This document contains information which may be changed at any time without notice