SLWS132 Datasheet, PDF (17/46 Pages) Texas Instruments – QUAD RECEIVER CHIP

GC4014 QUAD RECEIVER CHIP
DATA SHEET REV 0.6
The link port’s timing is as follows: The GC4014 checks the state of the ACK pin at the start of an OSP. If
ACK is low, the chip does nothing. If ACK is high, then the chip will transmit one, two or four complex words out of
the link port. The words are either the channel outputs or the sums of channels depending upon the summation
mode settings. The number of outputs transmitted is determined by the MUX_MODE settings. If MUX_MODE is 0,
only OUT_A will be transmitted. If MUX_MODE is 1, then OUT_A and OUT_B will be transmitted. If MUX_MODE is 2,
then all four will be transmitted. See Table 1 for a definition of OUT in the summation modes.
The data is transmitted in four bit nibbles on the rising edge of the bit clock. The transmission is completed
in 8, 16 or 32 clocks to transmit one, two or four complex pairs. If the ACK signal is low at the end of a word (after
clocks 8, 16, 24 and 32), then the clock will remain high and the transmission of the next word will be delayed until
ACK goes high again. If the ACK signal is low at the start of an OSP, then the transmission will be held off until the
next OSP. The clock remains low at the end of the transmission until the next OSP starts. The bit clock rate is
programmable as a division of the chip’s clock.
3.7 CLOCKING
The chip can be clocked in one of two modes. In the standard mode, the clock rate is equal to the input data
rate which can be up to 62.5 MHz. An internal clock doubler doubles the clock rate so that the internal circuitry is
clocked at twice the data rate. To use the standard mode the CKMODE pin must be grounded and the internal
control register bit EN_DOUBLER must be set high (See Section 5.10).
The alternate clock mode (pin CKMODE is high) accepts a double rate clock on the CK2X pin and bypasses
the clock doubler circuit. The EN_DOUBLER control bit should be low. In the alternate mode the user must provide
both the standard clock and the double rate clock.
3.8 POWER DOWN MODES
The chip has a power down and keep alive circuit. This circuit contains a slow, nominally 1 KHz, oscillator
and a clock-loss detect cell. This circuit is used to detect the loss of clock and provide a slow keep-alive clock to the
chip. The circuit is also used to power down the chip by switching from the high speed input clock to the low speed
keep-alive clock. The low speed clock rate is slow enough to power down the chip while fast enough to refresh the
dynamic nodes within the chip. The user can select whether this circuit is in the automatic clock-loss detect mode,
is always on (power down mode), or is disabled (the slow clock never kicks in). The whole chip, or individual down
converter channels can be powered down. Using the power down mode for individual channels can save significant
power.
3.9 SYNCHRONIZATION
Each GC4014 chip can be synchronized through the use of a sync input signal, an internal one shot sync
generator, or a sync counter. Each circuit within the chip, such as the sine/cosine generators or the decimation
GRAYCHIP, INC.
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APRIL 27, 1999
This document contains information which may be changed at any time without notice