SLWS132 Datasheet, PDF (24/46 Pages) Texas Instruments – QUAD RECEIVER CHIP

GC4014 QUAD RECEIVER CHIP
DATA SHEET REV 0.6
5.4 SCALE CONTROL REGISTER
Register 4 controls the CIC filter gain for the chip. These settings are common to all channels
ADDRESS 4:
CIC Scale, suggested default = 0x71
BIT
TYPE
NAME
DESCRIPTION
0-2
R/W
SCALE
SCALE ranges from 0 to 5.
3
R/W
unused
4-6
R/W
BIG_SCALE
BIG_SCALE ranges from 0 to 7.
7
R/W
unused
The CIC filter has a gain which is equal to N⁴. To remove this gain the CIC inputs are pre-scaled down by
(56-SCALE-6*BIG_SCALE) bits before filtering. The overall gain of each channel is equal to:
GAIN
=
{ N ⁴ 2 ^{( SCALE}
+
6
×
BIG_SCALE
–
56 ) _{} [}
2 ^COARSE ] { 1.0
+
NARROW
×
0.97
}
{
P_---F_--I_-R_---__--S_--U_---M_--
65536
}
[
3-G--2--
]
where COARSE and G are unique for each channel (See Section 5.17). PFIR_SUM is the sum of the 63 PFIR
coefficients if FILTER_SELECT in Register 1 is set, and NARROW is the CFIR narrow mode bit in Register 13. The
values of SCALE and BIG_SCALE must be such that the term in braces is less than unity, i.e.,
(SCALE + 6 × BIG_SCALE) ≤ (56 – 4log₂N) . Overflows due to improper gain settings will go undetected if this
relationship is violated. For example, this restriction means that BIG_SCALE and SCALE should be less than or
equal to 7 and 2 respectively for N equal to 8. The BIG_SCALE and SCALE settings are common to all channels.
See Section 7.9 for a discussion on how to optimally set the gain of the chip.
5.5 CHANNEL GAIN REGISTER
Register 5 contains the most significant 2 bits of each channel’s gain setting G. The least significant bits are
stored in each channel’s control page (See Section 5.17).
ADDRESS 5:
Channel Gain, suggested default = 0x00
BIT
TYPE
NAME
DESCRIPTION
0,1
R/W
GA[8:9]
3,4
R/W
GB[8:9]
4,5
R/W
GC[8:9]
6,7
R/W
GD[8:9]
2 MSBs of Channel A’s gain.
2 MSBs of Channel B’s gain.
2 MSBs of Channel C’s gain.
2 MSBs of Channel D’s gain.
Since the gain is G/32, and these bits are only used if G is greater than 256 (except for negative values),
then setting this register to zero still allows the user to add up to 18 dB of gain by just using the 8 LSB’s set in the
channel control pages. If more than 18 dB is desired, then these control register bits can be used. See Section 7.9
for a discussion on how to optimally set the gain of the chip.
GRAYCHIP, INC.
- 19 -
APRIL 27, 1999
This document contains information which may be changed at any time without notice