SLWS132 Datasheet, PDF (40/46 Pages) Texas Instruments – QUAD RECEIVER CHIP

GC4014 QUAD RECEIVER CHIP
DATA SHEET REV 0.6
The suggested DAMPS control register settings for the chip with an input sample rate of 49.7664 MHz
(N=128) is shown in the following table (other input rates can be used up to 62.5 MHz, 49.7664 is used as an
example):
Table 12: DAMPS Configuration
Control Registers
Channel pages 4,5,6,7
Coefficient Pages
Address
Data
Address
Data
Page 8
Page 9
Page 10
Page 11
00 (HEX)
65 (HEX)¹
10 (HEX)
FREQ[0:7]
08
27
00
AA
01
80->82²
11
FREQ[8:15]
01
FD
03
04
02
7F
12
FREQ[16:23] 8E
46
6C
29
03
00
13
FREQ[24:31] 01
FE
FD
18
04
43
14
00 (HEX)
9D
55
BD
05
05
00
15
00
01
00
F6
2F
06
11
16
12
1E
FE
37
FC
07
00
17
00
01
02
F0
46
08
50
18
5F
22
AB
6B
73
09
55
19
00
05
EB
5D
0A
FF
1A
E2
A2
F8
CA
0B
FF
1B
FE
07
E9
6F
0C
08
1C
0D
1P³
1D
B8
26
FD
08
3F
CB
ED
7B
0E
00
1E
07
AC
1C
F7
0F
read only
1F
FD
06
F6
7F
1. Initialize to 65 while configuring the chip(s), then set to E5, then back to 65 to fire off the one-shot sync.This
assumes that SO is tied to SI
2. Initialize to 80, then set to 82 after external coefficients are loaded.
3. “P” is the page number. The upper nibble should stay at “1¨.
The variables SCALE, BIG_SCALE (address 4) and G (address 16_HEX of pages 4,5,6,and 7) are set as
follows. The values of SCALE and BIG_SCALE must be set to satisfy: (SCALE + 6 × BIG_SCALE) ≤ (56 – 4log₂N) . N is
128, so (4log₂N) is 28. This means (SCALE + 6 × BIG_SCALE) ≤ 28 , which is satisfied by setting SCALE=4 and
BIG_SCALE=4. SCALE, however, needs to be decreased to 3 to prevent overflow in the CFIR, which has a gain of
1.97. The overall gain is set using “G” according to:
GAIN
=
{128⁴2^{(27 – 56)}}[
2^COARSE
]
(
1.97
)
(
P_---F_--I_-R_---__--S_--U_---M_--
65536
)
3^-G--2^-
=
0.113G
Where COARSE is 0 (see Section 7.9) and PFIR_SUM is 240593. The optimal setting of GAIN is 2.0 in order to
compensate for the loss in the tuning process (See Section 7.9). A value of G=18 (12_HEX) will give a gain of 2.034.
The output serial format is set in address 6 to have a bit rate of one half the chip’s clock rate and to be used
in the packed mode. The user will need to configure the output format as is necessary for the application.
GRAYCHIP, INC.
- 35 -
APRIL 27, 1999
This document contains information which may be changed at any time without notice