SLWS132 Datasheet, PDF (21/46 Pages) Texas Instruments – QUAD RECEIVER CHIP

GC4014 QUAD RECEIVER CHIP
DATA SHEET REV 0.6
5.0 CONTROL REGISTERS
The chip is configured and controlled through the use of eight bit control registers. These registers are
accessed for reading or writing using the control bus pins (CE, RD, WR, A[0:4], and C[0:7]) described in the
previous section. The register names and their addresses are:
The Mode and Control Registers are addresses 0 to 15
ADDRESS NAME
ADDRESS
NAME
0
Sync Mode
1
Decimation Mode
2
Decimation Byte 0
3
Decimation Byte 1
4
Scale Control
5
Channel Gain
6
Output Format
7
Output Mode
8
Blank Control
9
Channel Flush Control
10
Counter Byte 0
11
Counter Byte 1
12
Test Mode
13
Page Map
14
Status
15
Checksum
Addresses 16 to 31 are used in sixteen pages as determined by the page select control bits in the page map
register. The page assignments are:
PAGE
0
1
2
3
4
5
6
7
NAME
Channel Outputs
Keepalive Status
unused
unused
Channel Control A
Channel Control B
Channel Control C
Channel Control D
PAGE
8
9
10
11
12
13
14
15
NAME
Coefficients 0 to 7
Coefficients 8 to 15
Coefficients 16 to 23
Coefficients 24 to 31
unused
unused
unused
unused
The following sections describe each of these registers. The type of each register bit is either R, W, or R/W
indicating whether the bit is read only, write only, or read/write. All bits are active high.
GRAYCHIP, INC.
- 16 -
APRIL 27, 1999
This document contains information which may be changed at any time without notice