SLWS132 Datasheet, PDF (38/46 Pages) Texas Instruments – QUAD RECEIVER CHIP

GC4014 QUAD RECEIVER CHIP
DATA SHEET REV 0.6
The suggested GSM control register settings for the chip with an input sample rate of 54.166 MHz (N=25)
is shown in Table 12 (other input rates can be used up to 62.5 MHz, 54.166 is used as an example):
Table 11: GSM Configuration
Control Registers
Channel pages 4,5,6,7
Coefficient Pages
Address
Data
Address
Data
Page 8
Page 9
Page 10
Page 11
00 (HEX)
65 (HEX)¹
10 (HEX)
FREQ[0:7]
EF
F1
74
66
01
80->82²
11
FREQ[8:15]
03
FD
08
F5
02
19
12
FREQ[16:23] C3
CD
D5
86
03
00
13
FREQ[24:31] F8
FA
07
00
04
60
14
00 (HEX)
4F
52
CB
A3
05
00
15
00
00
FA
05
0F
06
11
16
2E
0F
C1
3D
A9
07
00
17
00
07
FB
00
20
08
50
18
5F
61
2F
24
86
09
55
19
06
FD
F9
32
0A
FF
1A
A7
6B
C2
71
0B
FF
1B
01
FF
F3
42
0C
08
1C
0D
1P³
1D
09
F0
8F
6D
01
03
F0
4C
0E
00
1E
AF
C1
50
81
0F
read only
1F
00
07
F0
4F
1. Initialize to 65 while configuring the chip(s), then set to E5, then back to 65 to fire off the one-shot sync.This
assumes that SO is tied to SI
2. Initialize to 80, then set to 82 after external coefficients are loaded.
3. “P” is the page number. The upper nibble should stay at “1¨.
The variables SCALE, BIG_SCALE (address 4) and G (address 16_HEX of pages 4,5,6,and 7) are set as
follows. The values of SCALE and BIG_SCALE must be set to satisfy: (SCALE + 6 × BIG_SCALE) ≤ (56 – 4log₂N) . N is
25, so (4log₂N) is 37.14. This means (SCALE + 6 × BIG_SCALE) ≤ 37 , which is satisfied by setting SCALE=1 and
BIG_SCALE=6. SCALE, however, needs to be decreased to 0 to prevent overflow in the CFIR, which has a gain of
1.97. The overall gain is set using “G” according to:
GAIN
=
{25⁴2^{(36 – 56)}}[
2^COARSE
]{
1.97
}
{
P_---F_--I_-R_---__--S_--U_---M_--
65536
}
-G----
32
= 0.0438G
Where COARSE is 0 and PFIR_SUM is 125151. The optimal setting of GAIN is 2.0 in order to compensate for the
loss in the tuning process (See Section 7.9). A value of G=46 (2E_HEX) will give a gain of 2.015.
The output serial format is set in address 6 to have a bit rate of one half the chip’s clock rate and to be used
in the packed mode. The user will need to configure the output format as is necessary for the application.
GRAYCHIP, INC.
- 33 -
APRIL 27, 1999
This document contains information which may be changed at any time without notice