SLWS132 Datasheet, PDF (20/46 Pages) Texas Instruments – QUAD RECEIVER CHIP

GC4014 QUAD RECEIVER CHIP
DATA SHEET REV 0.6
SIGNAL
DESCRIPTION
AIN, BIN, CIN, DIN
INPUT DATA, Active high
The 14 bit 2’s complement input data for the four channels. The data is clocked into the chip on the rising edge
of the clock (CK). The LSBs of DIN are used as the LSBs of AIN, BIN and CIN in the16 bit input mode (the pins
DIN0/AIN-2, DIN2/BIN-2 and DIN4/CIN-2 are the LSBs of the 16 bit AIN, BIN and CIN inputs).
AOUT, BOUT, COUT, DOUT
BIT SERIAL OUTPUT DATA, Active high
The bit serial output data are transmitted on these pins. In the serial mode these are individual outputs, in the link
mode these form a four bit nibble (DOUT/L0 is the LSB of the Nibble, AOUT/L3 is the MSB). The output bits are
clocked out on the rising edge of SCK (falling edge if SCK_POL=1). These pins are tri-stated at power up and are
enabled by the OUTPUT_ENABLE control register bit.
SCK
BIT SERIAL DATA CLOCK, Active high or low
The serial data bits are clocked out of the chip by this clock. The active edge of the clock is user programmable.
This pin is tri-stated at power up and is enabled by the OUTPUT_ENABLE control register bit.
SFS
BIT SERIAL FRAME STROBE, Active high or low
The bit serial word strobe. This strobe delineates the 16 or 32 bit words within the bit serial output streams. This
strobe is a pulse at the beginning of each bit serial word. The polarity of this signal is user programmable. This
pin is tri-stated at power up and is enabled by the OUTPUT_ENABLE control register bit.
RDY/ACK
READY OR ACKNOWLEDGE FLAG, programmable active high or low
The chip asserts this signal in the serial output mode to identify the beginning of an output sample period (OSP).
The width in input clock cycles and polarity of this signal are user programmable. This signal is typically used as
an interrupt to a DSP chip, but can also be used as a start pulse to dedicated circuitry. In the link mode this pin is
an input pin and is tied to the LACK handshake output from an ADSP-2106x SHARC DSP link port. This pin is
tri-stated at power up and is enabled in the serial mode by the OUTPUT_ENABLE control register bit.
CK
INPUT CLOCK. Active high
The clock input to the chip. The AIN, BIN, CIN, DIN and SI input signals are clocked into the chip on the rising
edge of this clock.
CK2X
DOUBLE RATE INPUT CLOCK. Active high
The double rate clock input to the chip. Used in the alternate clock mode to clock the chip. This clock must be
exactly twice the frequency of the CK clock. Should be grounded in the normal clock mode.
CKMODE
CLOCK MODE, Active high
The clock mode control. The chip uses CK2X when this pin is tied high (alternate mode) to clock the internal
circuitry. When this signal is grounded (normal mode) the chip doubles the CK clock to use as the internal clock.
SI
SYNC IN. Active low
The sync input to the chip. All timers, accumulators, and control counters are, or can be, synchronized to SI. This
sync is clocked into the chip on the rising edge of the input clock (CK).
SO
SYNC OUT. Active low
This signal is either a delayed version of the input sync SI, the sync counter’s terminal count (TC), or a one-shot
strobe. The SO signal is clocked out of the chip on the rising edge of the input clock (CK).
C[0:7]
CONTROL DATA I/O BUS. Active high
This is the 8 bit control data I/O bus. Control register data is loaded into the chip or read from the chip through
these pins. The chip will only drive these pins when CE is low and RD is low and WR is high.
A[0:4]
CONTROL ADDRESS BUS. Active high
These pins are used to address the control registers within the chip. Each of the control registers within the chip
are assigned a unique address. A control register can be written to or read from by setting A[0:4] to the register’s
address.
RD
READ ENABLE. Active low
This pin enables the chip to output the contents of the selected register on the C[0:7] pins when CE is also low.
WR
WRITE ENABLE. Active low
This pin enables the chip to write the value on the C[0:7] pins into the selected register when CE is also low.
CE
CHIP ENABLE. Active low
This control strobe enables the read or write operation. The contents of the register selected by A[0:4] will be
output on C[0:7] when RD is low and CE is low. If WR is low and CE is low, then the selected register will be
loaded with the contents of C[0:7].
Vup
MICROPROCESSOR INTERFACE POWER SUPPLY. Power Supply
This pin provides power for the microprocessor interface to allow it to interface to 5 volt logic. Input pins (A[0:4],
RD,WR,CE,C[0:7], and RDY/ACK) must not be driven above Vup+0.3V. The output pins (C[0:7], RDY/ACK) will
drive a logic one to Vup under no load.
GRAYCHIP, INC.
- 15 -
APRIL 27, 1999
This document contains information which may be changed at any time without notice