BQ24188_15 Datasheet, PDF (30/52 Pages) Texas Instruments – bq24188 2A, 30V, Host-Controlled Single-Input, Single Cell Switchmode Li-Ion Battery Charger with Power Path Management and USB-OTG Support

bq24188
SLUSC44A – DECEMBER 2014 – REVISED MAY 2015
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9.6.2 Control Register (READ/WRITE)
Memory location: 01, Reset state: 1xxx 1100
Figure 20. Control Register
B7(MSB)
B6
B5
B4
B3
B2
B1
B0(LSB)
1
X
X
X
1
1
0
.0
W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
BIT
B7(MSB)
FIELD
RESET
B6
IN_LIMIT_2
B5
IN_LIMIT_1
B4
IN_LIMIT _0
B3
B2
B1
B0(LSB)
EN_STAT
TE
CE
HZ_MODE
TYPE
W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
DESCRIPTION
Write: 1-Reset all registers to default values
0-No effect
Read: always get “1”
000-USB2.0 host with 100mA current limit
001-USB3.0 host with 150mA current limit
010 – USB2.0 host with 500mA current limit
011 – USB3.0 host/charger with 900mA current limit
100 – Charger with 1500mA current limit
101—Charger with 1950mA current limit
110 – Charger with 2500mA current limit
111- Charger with 2000mA current limit (default 000⁽¹⁾)
0-Disable STAT function (STAT only shows faults)
1-Enable STAT function (default 1)
0-Disable charge current termination
1-Enable charge current termination (default 1)
0-Charger enabled
1-Charger is disabled (default 0)
0-Not high impedance mode
1-High impedance mode (default 0)
(1) When in DEFAULT mode, PSEL determines the default input current limit.
RESET Bit
The RESET bit in the control register (0x01h) is used to reset all the charge parameters. Write “1” to
RESET bit to reset all the registers to default values and place the bq24188 into DEFAULT mode and turn
off the watchdog timer. The RESET bit is automatically cleared to zero once the bq24188 enters
DEFAULT mode.
CE Bit (Charge Enable)
The CE bit is used to disable or enable the charge process. A low logic level (0) on this bit enables the
charge and a high logic level (1) disables the charge. When charge is disabled, the SYS output regulates
to V_SYS(REG) and battery is disconnected from the SYS. Supplement mode is available if the system load
demands cannot be met by the supply.
HZ_MODE Bit (High Impedance Mode Enable)
The HZ_MODE bit is used to disable or enable the high impedance mode. A low logic level (0) on this bit
enables the IC and a high logic level (1) puts the IC in a low quiescent current state called high
impedance mode. When in high impedance mode, the converter is off and the battery FET and BGATE
are on. The load on SYS is supplied by the battery. BGATE is low (external FET turned on) while in high
impedance mode.
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