BQ24188_15 Datasheet, PDF(18/52 Page) Texas Instruments – bq24188 2A, 30V, Host-Controlled Single-Input, Single Cell Switchmode Li-Ion Battery Charger with Power Path Management and USB-OTG Support

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BQ24188_15 Datasheet, PDF (18/52 Pages) Texas Instruments – bq24188 2A, 30V, Host-Controlled Single-Input, Single Cell Switchmode Li-Ion Battery Charger with Power Path Management and USB-OTG Support

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bq24188

SLUSC44A â DECEMBER 2014 â REVISED MAY 2015

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Device Functional Modes (continued)

current limit, VIN-DPM, or 100% duty cycle), the SYS output drops to the VMINSYS output voltage. When this

happens, the charge current is reduced to ensure the system is supplied with all the current that is needed while

maintaining the minimum system voltage. If the charge current is reduced to 0mA, pulling further current from

SYS causes the output to fall to the battery voltage and enter supplement mode (see the âDynamic Power Path

Managementâ section for more details).

Once the battery is charged enough that the system voltage rises above VSYSREG(LO) (approximately 3.5V), the

battery FET is turned on fully and the battery is charged with the full programmed charge current set by the I2C

interface, ICHARGE. The charge current is regulated to ICHARGE until the voltage between BAT and PGND reaches

the regulation voltage. The voltage between BAT and PGND is regulated to VBATREG (CV mode) while the charge

current naturally tapers down as shown in Figure 10. During CV mode, the SYS output remains connected to the

battery. The impedance of the battery FET is increased to 4x of the fully on value when IBAT falls below ~350mA

to provide increased accuracy during termination. This will show a small rise in the SYS voltage when the RDSON

increases below ~350mA.

When termination is enabled (TE bit is '1'), the bq24188 monitors the charging current during the CV mode. Once

the charge current tapers down to the termination threshold, ITERM, and the battery voltage is above the recharge

threshold, the bq24188 terminates charge, turns off the battery charging FET and enters battery detection (see

Battery Detection section for more details). The system output is regulated to the VSYSREG(HI) and supports the full

current available from the input. The battery supplement mode is available to supply any SYS load that cannot

be supported by the input source (see the âDynamic Power Path Managementâ section for more details). The

termination current level is programmable. To disable the charge current termination, the host sets the charge

termination bit (TE) of charge control register to 0. Refer to I2C section for details. When termination is disabled,

VBAT is continuously regulated to VBATREG. Termination is also disabled when any loop is active other than CC or

CV. This includes VINDPM, input current limit, or thermal regulation. Termination is also disabled during TS

warm/cool conditions and when the LOW_CHG bit is set to '1'.

A charge cycle is initiated when one of the following conditions is detected:

1. The battery voltage falls below the VBATREG-VRCH threshold.

2. IN Power-on reset (POR)

3. CE bit toggle or RESET bit is set (Host controlled)

4. CD terminal is toggled

9.4.5 Charge Time Optimizer

The CC to CV transition is enhanced in the bq24188 architecture. The "knee" between CC and CV is sharp. This

enables the charger to remain in CC mode as long as possible before beginning to taper the charge current (CV

mode). This provides a decrease in charge time as compared to older topologies.

9.4.6 Battery Detection

When termination conditions are met, a battery detection cycle is started. During battery detection, IDETECT is

pulled from VBAT for tDETECT(SNK) to verify there is a battery. If the battery voltage remains above VDET(SINK) for the

full duration of tDETECT(SNK), a battery is determined to present and the IC enters âCharge Doneâ. If VBAT falls

below VDET(SINK), a âBattery Not Presentâ fault is signaled, the charge parameters are reset (VBATREG, ICHARGE and

ITERM) and battery detection continues. The next cycle of battery detection, the bq24188 turns on IBATSHRT for

tDETECT(SRC). If VBAT rises to VDET(SRC1), the current source is turned off and a âNo Batteryâ condition is registered.

In order to keep VBAT high enough to close the battery protector, the current source turns on if VBAT falls to

VDET(SRC2). The source cycle continues for tDETECT(SRC). After tDETECT(SRC), the battery detection continues through

another current sink cycle. Battery detection continues until charge is disabled, the bq24188 enters high-z mode

or a battery is detected. Once a battery is detected, the fault status clears and a new charge cycle begins. With

no battery connected, the BAT output will transition from VRCH to PGND with a high period of tDETECT(SRC) and a

low period of tDETECT(SNK). See Figure 29 in the Application Curves section. Battery detection is not performed

when termination is disabled.

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