BQ24188_15 Datasheet, PDF (26/52 Pages) Texas Instruments – bq24188 2A, 30V, Host-Controlled Single-Input, Single Cell Switchmode Li-Ion Battery Charger with Power Path Management and USB-OTG Support

bq24188
SLUSC44A – DECEMBER 2014 – REVISED MAY 2015
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9.5 Programming
9.5.1 Serial Interface Description
The bq24188 uses an I²C compatible interface to program charge parameters. I²C is a 2-wire serial interface
developed by NXP (formerly Philips Semiconductor, see I²C-Bus Specification, Version 5, October 2012). The
bus consists of a data line (SDA) and a clock line (SCL) with pull-up structures. When the bus is idle, both SDA
and SCL lines are pulled high. All the I²C compatible devices connect to the I²C bus through open drain I/O
terminals, SDA and SCL. A master device, usually a microcontroller or a digital signal processor, controls the
bus. The master is responsible for generating the SCL signal and device addresses. The master also generates
specific conditions that indicate the START and STOP of data transfer. A slave device receives and/or transmits
data on the bus under control of the master device.
The bq24188 device works as a slave and supports the following data transfer modes, as defined in the I²C
Bus™ Specification: standard mode (100 kbps) and fast mode (400 kbps). The interface adds flexibility to the
battery charge solution, enabling most functions to be programmed to new values depending on the
instantaneous application requirements. The I²C circuitry is powered from IN when a supply is connected. If the
IN supply is not connected, the I²C circuitry is powered from the battery through BAT. The battery voltage must
stay above V_BATUVLO with no input connected in order to maintain proper operation.
The data transfer protocol for standard and fast modes is exactly the same; therefore, they are referred to as the
F/S-mode in this document. The device only supports 7-bit addressing. The device 7-bit address is defined as
‘1101011’ (0x6Bh).
To avoid I²C hang-ups, a timer (t_I2CRESET) runs during I2C transactions. If the transaction takes longer than
t_I2CRESET, any additional commands are ignored and the I2C engine is reset. The timeout is reset with START
and repeated START conditions and stops when a valid STOP condition is sent.
9.5.2 F/S Mode Protocol
The master initiates data transfer by generating a start condition. The start condition is when a high-to-low
transition occurs on the SDA line while SCL is high, as shown in Figure 15. All I²C -compatible devices should
recognize a start condition.
DATA
CLK
S
P
START Condition
STOP Condition
Figure 15. START and STOP Condition
The master then generates the SCL pulses, and transmits the 8-bit address and the read/write direction bit R/W
on the SDA line. During all transmissions, the master ensures that data is valid. A valid data condition requires
the SDA line to be stable during the entire high period of the clock pulse (see Figure 16). All devices recognize
the address sent by the master and compare it to their internal fixed addresses. Only the slave device with a
matching address generates an acknowledge (see Figure 17) by pulling the SDA line low during the entire high
period of the ninth SCL cycle. Upon detecting this acknowledge, the master knows that communication link with a
slave has been established.
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