BQ24188_15 Datasheet, PDF (27/52 Pages) Texas Instruments – bq24188 2A, 30V, Host-Controlled Single-Input, Single Cell Switchmode Li-Ion Battery Charger with Power Path Management and USB-OTG Support

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Programming (continued)
DATA
bq24188
SLUSC44A – DECEMBER 2014 – REVISED MAY 2015
CLK
Data Line
Stable;
Data Valid
Change
of Data
Allowed
Figure 16. Bit Transfer on the Serial Interface
The master generates further SCL cycles to either transmit data to the slave (R/W bit 0) or receive data from the
slave (R/W bit 1. In either case, the receiver needs to acknowledge the data sent by the transmitter. So an
acknowledge signal can either be generated by the master or by the slave, depending on which one is the
receiver. The 9-bit valid data sequences consisting of 8-bit data and 1-bit acknowledge can continue as long as
necessary. To signal the end of the data transfer, the master generates a stop condition by pulling the SDA line
from low to high while the SCL line is high (see Figure 15). This releases the bus and stops the communication
link with the addressed slave. All I2C compatible devices must recognize the stop condition. Upon the receipt of
a stop condition, all devices know that the bus is released, and wait for a start condition followed by a matching
address. If a transaction is terminated prematurely, the master needs to send a STOP condition to prevent the
slave I2C logic from remaining in a incorrect state. Attempting to read data from register addresses not listed in
this section will result in 0xFFh being read out.
Data Output
by Transmitter
Data Output
by Receiver
SCL From
Master
START
Condition
Not Acknowledge
Acknowledge
1
2
8
9
Clock Pulse for
Acknowledgement
Figure 17. Acknowledge on the I2C Bus
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