OMAP5912ZZG Datasheet, PDF (254/269 Pages) Texas Instruments – This data sheet revision history highlights the technical changes made to SPRS231D to generate SPRS231E

Electrical Specifications
5.18 MICROWIRE Interface Timing
Table 5−39 and Table 5−40 assume testing over recommended operating conditions (see Figure 5−52).
Table 5−39. MICROWIRE Timing Requirements
NO.
MIN MAX UNIT
W5 t_su(SDI-SCLK)
Setup time, UWIRE.SDI valid before UWIRE.SCLK active edge^†
16
ns
W6 t_h(SCLK-SDI)
Hold time, UWIRE.SDI invalid after UWIRE.SCLK active edge^†
1
ns
† _{Polarity of UWIRE.SCLK and the active clock edge (rising or falling) on which SDO data is driven and SDI data is latched is all}
software-configurable. These timings apply to all configurations regardless of UWIRE.SCLK polarity and which clock edges are used to drive
output data and capture input data.
Table 5−40. MICROWIRE Switching Characteristics
NO.
PARAMETER
MIN MAX UNIT
W1 f_op(SCLK)
W2 t_w(SCLK)
Operating frequency, UWIRE.SCLK
Pulse duration, UWIRE.SCLK high/low
0.25B^‡ MHz
0.45P^§ 0.55P^§ ns
W3 t_d(SCLK-SDO)
Delay time, UWIRE.SCLK active edge to UWIRE.SDO transition^†
−2
6 ns
W4 t_d(CS-SCLK)
Delay time, UWIRE.CSx active to UWIRE.SCLK active^†
1.5P^§
ns
† _{Polarity of UWIRE.SCLK and the active clock edge (rising or falling) on which SDO data is driven and SDI data is latched is all}
software-configurable. These timings apply to all configurations regardless of UWIRE.SCLK polarity and which clock edges are used to drive
output data and capture input data.
‡ _{B = system clock of the OMAP5912 (12, 13, or 19.2 MHz).}
§ _{P = UWIRE.SCLK cycle time in nanoseconds (ns).}
UWIRE.CSx
W4
UWIRE.SCLK
W2
W2
[1/W1]
W4
UWIRE.SDO
UWIRE.SDI
W3
W3
Valid Valid Valid
W5
W6
Valid Valid Valid
NOTE: The polarities of UWIRE.CSx and UWIRE.SCLK and the active UWIRE.SCLK edges on which SDO is driven and SDI is sampled are
all software-configurable.
Figure 5−52. MICROWIRE Timings
254 SPRS231E
December 2003 − Revised December 2005