OMAP5912ZZG Datasheet, PDF (198/269 Pages) Texas Instruments – This data sheet revision history highlights the technical changes made to SPRS231D to generate SPRS231E

Electrical Specifications
5.2 Recommended Operating Conditions (Continued)
MIN
NOM
MAX
UNIT
High-level ^{Low-voltage range DVDDmin = 1.65 V}
I_OH
output
High-voltage range DV_DDmin = 2.5 V
current
18.3-mA drive strength buffers
−2
mA
−3
mA
−18.3
mA
Low-level ^{Low-voltage range DVDDmin = 1.65 V}
I_OL
output
High-voltage range DV_DDmin = 2.5 V
current
18.3-mA drive strength buffers
2
3
mA
18.3
T_C
Operating case temperature
−40
85
°C
† _{All core voltage supplies must be tied to the same voltage level (within 50 mV).}
‡ _{In Split-power mode (CVDDx and DVDDx = 0), RTC has to be supplied with CVDDRTC = 1.05 V min and DVDDRTC = 1.65 V min.}
§ _{Low-power standby is defined as follows: the device is in deep-sleep mode and LOW_PWR = 1. The device runs from 32-kHz clock in this}
mode.
¶ _{To filter switching noises, it is recommended that an RC (R = 10 Ω, C = 100 nF) low-pass filter be implemented externally.}
# _{Corresponding DVDD mode bit must be configured in the Voltage_control_0 register.}
|| _{In systems where the CVDDx and DVDDx power supplies are ramped at generally the same time (within 500 ms of one another), there are no}
specific power sequencing requirements for the supplies. The only sequencing requirement is that the maximum voltage difference between
CV_DD and DV_DD is not exceeded for greater than 500 ms. Likewise, if different voltages are used for the separate DV_DDx supplies, all DV_DDx
supplies should be ramped up to valid voltage levels within 500 ms of one another.
kAn external capacitor (C = 1 µF ± 10%) must be connected between LDO.FILTER and V_SS to provide decoupling capacitance for the regulator.
hLDO has to be powered down by setting LDO_PWRDN_CNTL[0] in OMAP5912 configuration.
198 SPRS231E
December 2003 − Revised December 2005