OMAP5912ZZG Datasheet, PDF (101/269 Pages) Texas Instruments – This data sheet revision history highlights the technical changes made to SPRS231D to generate SPRS231E

Functional Overview
3.1 Functional Block Diagram Features
The OMAP5912 devices include the following functional blocks:
• ARM926EJS megacell including:
− ARM926EJS, supporting the operating system
− MMU with translation lookaside buffer (TLBx)
− L1 16K-byte, four-way, set-associative instruction cache
− L1 8K-byte, four-way, set-associative data cache with write buffer
• MPU interrupt handler level 1
• Embedded trace macrocell module, ETM version 2.a in a 13-bit mode configuration or in a 17-bit
demultiplexed mode configuration
• C55x DSP subsystem:
− Embedded ICE emulator interface through JTAG port
− TMS320C55x (C55x) DSP rev 2.1
− L1 cache (24K bytes)
− 16K-byte, two-way, set-associative instruction cache
− 2 × 4K-byte RAM set for instruction
− DARAM 64K-byte, zero-wait state, 32-bit organization
− SARAM 96K-byte, zero-wait state, 32-bit organization
− PDROM (32K bytes)
− DMA controller: Six physical channels, five ports
− DSP trace module
− Hardware accelerators motion estimation (ME), discrete/inverse discrete cosine transform
(DCT/IDCT), and pixel interpolation (PI)
− DSP interrupt handler level 1 in the C55x DSP core
• DSP MMU
• DSP level 2 interrupt handler enabling connection to 16 additional interrupt lines outside OMAP. The
priority of each interrupt line is controlled by software.
• DSP interrupt interface enabling connection to the interrupt lines coming out of the level 2 interrupt handler
and the interrupt lines requiring higher priority. The outcome interrupt of this module is then connected
to the DSP megacell to be processed by the DSP. This module mainly ensures that all interrupts going
to the DSP megacell are level-sensitive.
• DSP peripherals:
− 3 × 16-bit DSP private timers
− 1 × 16-bit DSP private watchdog
• Mailboxes:
Four mailboxes are implemented:
− Two read/write accessible by MPU, read-only by the DSP
− Two read/write accessible by the DSP, read-only by the MPU
Each mailbox is implemented with 2 × 16-bit registers. When a write is done into a register by one
processor, it generates an interrupt; this interrupt is released by the read access of the other processor.
December 2003 − Revised December 2005
SPRS231E 101