OMAP5912ZZG Datasheet, PDF (132/269 Pages) Texas Instruments – This data sheet revision history highlights the technical changes made to SPRS231D to generate SPRS231E

Functional Overview
DSP WORD
ADDRESS
0x00 8000h
0x00 8000h
0x00 8000h
0x00 8001h
0x00 8001h
0x00 8002h
0x00 8002h
0x00 8002h
0x00 8003h
0x00 8004h
0x00 8004h
0x00 8005h
0x00 8005h
0x00 8006h
0x00 8006h
0x00 8006h
0x00 8007h
0x00 8007h
0x00 8007h
0x00 8008h
0x00 8009h
0x00 800Ah
0x00 800Ah
0x00 800Bh
0x00 800Bh
0x00 800Ch
0x00 800Ch
0x00 800Dh
0x00 800Dh
0x00 800Eh
0x00 800Eh
0x00 800Fh
0x00 8010h
0x00 8011h
0x00 8012h
0x00 8013h
0x00 8014h
0x00 8015h
0x00 8016h
0x00 8017h
MPU BYTE
ADDRESS
FFFB:0000
FFFB:0000
FFFB:0000
FFFB:0004
FFFB:0004
FFFB:0008
FFFB:0008
FFFB:0008
FFFB:000C
FFFB:0010
FFFB:0010
FFFB:0014
FFFB:0014
FFFB:0018
FFFB:0018
FFFB:0018
FFFB:001C
FFFB:001C
FFFB:001C
FFFB:0020
FFFB:0024
FFFB:0028
FFFB:0028
FFFB:002C
FFFB:002C
FFFB:0030
FFFB:0030
FFFB:0034
FFFB:0034
FFFB:0038
FFFB:0038
FFFB:003C
FFFB:0040
FFFB:0044
FFFB:0048
FFFB:004C
FFFB:0050
FFFB:0054
FFFB:0058
FFFB:005C
Table 3−26. UART1 Registers
REGISTER
NAME
DESCRIPTION
UART1_RHR
UART1 receive holding register
UART1_THR
UART1 transmit holding register
UART1_DLL
UART1 divisor latch low register
UART1_IER
UART1 interrupt enable register
UART1_DLH
UART1 divisor latch high register
UART1_IIR
UART1 interrupt identification register
UART1_FCR
UART1 FIFO control register
UART1_EFR
UART1 enhanced feature register
UART1_LCR
UART1 line control register
UART1_MCR
UART1 modem control register
UART1_XON1
UART1 XON1 register
UART1_LSR
UART1 mode register
UART1_XON2
UART1 XON2 register
UART1_MSR
UART1 modem status register
UART1_TCR
UART1 transmission control register
UART1_XOFF1
UART1 XOFF1 register
UART1_SPR
UART1 scratchpad register
UART1_TLR
UART1 trigger level register
UART1_XOFF2
UART1 XOFF2 register
UART1_MDR1
UART1 mode definition 1 register
UART1_MDR2
UART1 mode definition register 2
UART1_SFLSR
UART1 status FIFO line status register
UART1_TXFLL
UART1 transmit frame length low
UART1_RESUME UART1 resume register
UART1_TXFLH
UART1 transmit frame length high
UART1_SFREGL
UART1 status FIFO low register
UART1_RXFLL
UART1 receive frame length low
UART1_SFREGH UART1 status FIFO high register
UART1_RXFLH
UART1 receive frame length high
UART1_UASR
UART1 autobauding status register
UART1_BLR
UART1 BOF control register
UART1_ACREG
UART1 auxiliary control register
UART1_SCR
UART1 supplementary control register
UART1_SSR
UART1 supplementary status register
UART1_EBLR
UART1 BOF length register
Reserved
UART1_MVR
UART1 module version register
UART1_SYSC
UART1 system configuration register
UART1_SYSS
UART1 system status register
UART1_WER
UART1 wake-up enable register
ACCESS ACCESS RESET
WIDTH TYPE
VALUE
8
R
Undefined
8
W
Undefined
8
R/W 00h
8
R/W 00h
8
R/W 00h
8
R
01h
8
W
00h
8
R/W 00h
8
R/W 00h
8
R/W 00h
8
R/W 00h
8
R
60h
8
R/W 00h
8
R
Undefined
8
R/W 0Fh
8
R/W 00h
8
R/W 00h
8
R/W 00h
8
R/W 00h
8
R/W 07h
8
R/W 00h
8
R
00h
8
W
00h
8
R
00h
8
W
00h
8
R
Undefined
8
W
00h
8
R
Undefined
8
W
00h
8
R
00h
8
R/W 40h
8
R/W 00h
8
R/W 00h
8
R
00h
8
R/W 00h
8
R
−
8
R/W 00h
8
R/W 00h
8
R/W 7Fh
132 SPRS231E
December 2003 − Revised December 2005