OMAP5912ZZG Datasheet, PDF (210/269 Pages) Texas Instruments – This data sheet revision history highlights the technical changes made to SPRS231D to generate SPRS231E

Electrical Specifications
Table 5−10. EMIFS/NOR Flash Interface Switching Characteristics^†‡ (Continued)
DV_DD5 = 1.8 V/2.75 V/3.3 V
NO
PARAMETER
NOMINAL
UNIT
MIN
MAX
F27/2 t_d(WEIV-AIV)
Delay time, FLASH.WE high to FLASH.A[25:1]
invalid
Async modes
P − 3.5
P + 6.3 ns
F27/3 t_d(WEIV-DIV)
Delay time, FLASH.WE high to FLASH.D[15:0]
invalid
Async modes
P − 4.4
P + 1.812 ns
F28 t_d(CSV-DLZ)
Delay time, FLASH.CSx low to data bus driven
Async modes
F29 t_d(CSV-DV)
Delay time, FLASH.CSx low to data bus valid
Async modes
F30 t_d(CSIV-DIV) Delay time, FLASH.CSx high to data bus invalid Async modes
F31 t_d(CSIV-DHZ) Delay time, FLASH.CSx high to data bus high Z Async modes
Delay time, FLASH.CLK high to FLASH.BAA
F35 t_{d(CLKH-BAA) transition}
Sync modes
−13.9
−12.9
−12.9
−13.9
I + 0.68
0.4 ns
2.19 ns
2.19 ns
0.4 ns
I + 8 ns
FLASH.CS0
Sync modes
H − 9.3
ns
F36
t_d(CSV-CLKV)
Delay time, FLASH.CSx low to FLASH.CLK high
FLASH.CS1,
FLASH.CS2,
FLASH.CS3
H − 8.1
ns
Sync modes
Delay time, FLASH.CLK invalid to FLASH.CSx
F37 t_{d(CLKIV-CSIV) high}
Sync modes
H + 0.1
ns
F40 t_d(OEV-DIV)
Delay time, FLASH.OE low to data bus invalid
Async and sync
modes
−4.8
0.64 ns
F41 t_d(OEV-DHZ) Delay time, FLASH.OE low to data bus high Z
Async and sync
modes
−8.9
0.5 ns
F42 t_d(WEV-DIV)
Delay time, FLASH.WE low to data bus invalid
Async and sync
modes
−4.5
1.93 ns
F43 t_d(WEV-DV)
Delay time, FLASH.WE low to data bus valid
Async and sync
modes
−4.5
1.93 ns
† _{The maximum EMIFS/flash clock rate is limited to the maximum traffic controller clock rate for the OMAP5912, provided all EMIFS/flash timing}
constraints are met.
‡ _{See Section 5.7.1.1 for information on and an example of how to calculate OMAP5912 EMIFS NOR Flash timings.}
A = (RDWST + 2) * EMIFS clock period (REF_CLK)
B = (ADVHOLD + 1) * EMIFS clock period (REF_CLK)
C = (RDWST – OEHOLD +2) * EMIFS clock period (REF_CLK)
D = (PGWST + 1) * EMIFS clock period (REF_CLK)
E = (WRWST + WELEN + 3) * EMIFS clock period (REF_CLK)
F = (WRWST + 1) * EMIFS clock period (REF_CLK)
G = (WELEN + 1) * EMIFS clock period (REF_CLK)
H = 1 * EMIFS clock period (REF_CLK)
I = 0.5 * EMIFS clock period (REF_CLK)
J = (BTWST + 1) * EMIFS clock period (REF_CLK)
K = OESETUP * EMIFS clock period (REF_CLK)
L = OEHOLD * EMIFS clock period (REF_CLK)
M = (ADVHOLD + 1) * EMIFS clock period (REF_CLK) + 1 TC_CK period
210 SPRS231E
December 2003 − Revised December 2005