71M6403 Datasheet, PDF (6/75 Pages) Teridian Semiconductor Corporation – Electronic Trip Unit

71M6403
Electronic Trip Unit
SEPTEMBER 2006
Table 23: The PCON Register ........................................................................................................................................... 26
Table 24: PCON Register Bit Description .......................................................................................................................... 26
Table 25: The IEN0 Register ............................................................................................................................................. 27
Table 26: The IEN0 Bit Functions...................................................................................................................................... 27
Table 27: The IEN1 Register ............................................................................................................................................. 27
Table 28: The IEN1 Bit Functions...................................................................................................................................... 27
Table 29: The IP0 Register ............................................................................................................................................... 28
Table 30: The IP0 bit Functions ........................................................................................................................................ 28
Table 31: The WDTREL Register....................................................................................................................................... 28
Table 32: The WDTREL Bit Functions ............................................................................................................................... 28
Table 33: The IEN0 Register ............................................................................................................................................. 29
Table 34: The IEN0 Bit Functions...................................................................................................................................... 29
Table 35: The IEN1 Register ............................................................................................................................................. 30
Table 36: The IEN1 Bit Functions...................................................................................................................................... 30
Table 37: The IEN2 Register ............................................................................................................................................. 30
Table 38: The IEN2 Bit Functions...................................................................................................................................... 30
Table 39: The TCON Register............................................................................................................................................ 31
Table 40: The TCON Bit Functions .................................................................................................................................... 31
Table 41: The IRCON Register .......................................................................................................................................... 31
Table 42: The IRCON Bit Functions................................................................................................................................... 31
Table 43: External MPU Interrupts.................................................................................................................................... 32
Table 44: Control Bits for External Interrupts.................................................................................................................... 32
Table 45: Priority Level Groups ........................................................................................................................................ 33
Table 46: The IP0 Register: .............................................................................................................................................. 33
Table 47: The IP1 Register: .............................................................................................................................................. 33
Table 48: Priority Levels ................................................................................................................................................... 33
Table 49: Interrupt Polling Sequence................................................................................................................................ 34
Table 50: Interrupt Vectors............................................................................................................................................... 34
Table 51: Direction Registers and Internal Resources for DIO Pin Groups........................................................................ 35
Table 52: DIO_DIR Control Bit .......................................................................................................................................... 35
Table 53: Selectable Controls using the DIO_DIR Bits ...................................................................................................... 36
Table 54: MPU Data Memory Map.................................................................................................................................... 36
Table 55: Liquid Crystal Display Segment Table (Typical)................................................................................................. 38
Table 56: EECTRL Status Bits ........................................................................................................................................... 41
Table 57: TMUX[3:0] Selections ....................................................................................................................................... 42
Table 58: SSI Pin Assignment .......................................................................................................................................... 43
Table 59: CHOP_EN Bits................................................................................................................................................... 48
Page: 6 of 75
© 2006 TERIDIAN Semiconductor Corporation
REV 1.0