71M6403 Datasheet, PDF (53/75 Pages) Teridian Semiconductor Corporation – Electronic Trip Unit

71M6403
Electronic Trip Unit
SEPTEMBER 2006
DIO_0[7:0]
DIO_1[7:0]
DIO_2[5:0]
DIO_FLT
DIO_STR
DIO_EEX
EEDATA[7:0]
EECTRL[7:0]
ECK_DIS
EX_XFR
EX_ZP8
FIR_LEN
FLASH66Z
FLSH_ERASE
FLSH_MEEN
FLSH_PGADR
SFR 80
SFR 90
SFR A0[5:0]
2008[2]
2008[3]
2008[4]
SFR 9E
SFR 9F
2005[5]
2002[0]
2002[1]
2005[4]
2005[1]
SFR 94
SFR B2[1]
SFR B7[7:1]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
W
W
W
Port 0
Port 1
Port 2
The value on the DIO pins. Pins configured as LCD will read
zero. When written, changes data on pins configured as out-
puts. Pins configured as LCD or input will ignore writes.
Causes FAULT_PULSE to be output on DIO7, if DIO7 is configured as
output. LCD_NUM must be less than 15. Initialize DIO_FLT to 1.
Causes STROBE to be output on DIO6, if DIO6 is configured as output.
LCD_NUM must be less than 16. Initialize DIO_STR to 1.
When set, converts DIO4 and DIO5 to interface with external
EEPROM. DIO4 becomes SCK and DIO5 becomes bi-directional SDA.
LCD_NUM must be less than 18.
Serial EEPROM interface data
Serial EEPROM interface control
Emulator clock disable. When one, the emulator clock is disabled.
Interrupt enable bits. These bits enable the XFER_BUSY and the ZP8
interrupts to the MPU. Note that if either interrupt is to be enabled, EX6
in the 80515 must also be set.
The length of the ADC decimation FIR filter.
1: 22 ADC bits/3 PLLOUT cycles (384 CKFIR cycles),
0: 21 ADC bits/2 PLLOUT cycles (288 CKFIR cycles)
Should be set to 1 to minimize supply current.
Flash Erase Initiate
FLSH_ERASE is used to initiate either the Flash Mass Erase cycle or
the Flash Page Erase cycle. Specific patterns are expected for
FLSH_ERASE in order to initiate the appropriate Erase cycle.
(default = 0x00).
0x55 – Initiate Flash Page Erase cycle. Must be preceded by a write to
FLSH_PGADR @ SFR 0xB7.
0xAA – Initiate Flash Mass Erase cycle. Must be preceded by a write to
FLSH_MEEN @ SFR 0xB2 and the debug (CC) port must be
enabled.
Any other pattern written to FLSH_ERASE will have no effect.
Mass Erase Enable
0 – Mass Erase disabled (default).
1 – Mass Erase enabled.
Must be re-written for each new Mass Erase cycle.
Flash Page Erase Address
FLSH_PGADR[6:0] – Flash Page Address (page 0 thru 127) that will be
erased during the Page Erase cycle. (default = 0x00).
Must be re-written for each new Page Erase cycle.
Page: 53 of 75
© 2006 TERIDIAN Semiconductor Corporation
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