71M6403 Datasheet, PDF (21/75 Pages) Teridian Semiconductor Corporation – Electronic Trip Unit

71M6403
Electronic Trip Unit
SEPTEMBER 2006
UART
The 71M6403 includes a UART (UART0) that can be programmed for general purpose communications. A second UART
(UART1) is connected to the optical port, as described in the optical port description.
The UART is a dedicated 2-wire serial interface, which can communicate with an external host processor at up to 38,400 bits/s
(with MPU clock = 1.2288MHz). The operation of each pin is as follows:
RX: Serial input data are applied at this pin. Conforming to RS-232 standard, the bytes are input LSB first. The voltage applied at
RX must not exceed 3.6V.
TX: This pin is used to output the serial data. The bytes are output LSB first.
The 71M6403 has several UART-related registers, which can be read and written. All UART transfers are programmable for
parity enable, parity, 2 stop bits/1 stop bit and XON/XOFF options for variable communication baud rates from 300 to 38400 bps.
Table 11 shows how the baud rates are calculated. Table 12 shows the selectable UART operation modes.
Serial Interface 0
Serial Interface 1
Using Timer 1
2^smod * f_CKMPU/ (384 * (256-TH1))
N/A
Using Internal Baud Rate Generator
2^smod * f_CKMPU/(64 * (2¹⁰-S0REL))
f_CKMPU/(32 * (2¹⁰-S1REL))
Note: S0REL and S1REL are 10-bit values derived by combining bits from the respective timer reload registers. SMOD is the
SMOD bit in the SFR PCON. TH1 is the high byte of timer 1.
Table 11: Baud Rate Generation
Mode 0
Mode 1
Mode 2
Mode 3
UART 0
N/A
Start bit, 8 data bits, stop bit,
variable baud rate (internal baud
rate generator or timer 1)
Start bit, 8 data bits, parity, stop bit,
fixed baud rate 1/32 or 1/64 of f_CKMPU
Start bit, 8 data bits, parity, stop bit,
variable baud rate (internal baud
rate generator or timer 1)
UART 1
Start bit, 8 data bits, parity, stop bit, variable
baud rate (internal baud rate generator)
Start bit, 8 data bits, stop bit, variable baud rate
(internal baud rate generator)
N/A
N/A
Table 12: UART Modes
Note: Parity of serial data is available through the P flag of the accumulator. Seven-bit serial modes with parity, such as those
used by the FLAG protocol, can be simulated by setting and reading bit 7 of 8-bit output data. Seven-bit serial modes without
parity can be simulated by setting bit 7 to a constant 1. 8-bit serial modes with parity can be simulated by setting and reading the
9^th bit, using the control bits S0CON3 and S1CON3 in the S0COn and S1CON SFRs.
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© 2006 TERIDIAN Semiconductor Corporation
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